Schematic Editor

#regulators 'LP2985LV' 'Package_TO_SOT_SMD:SOT-23-5_HandSoldering' ```

==== 查看当前封装

The Footprint Assignment Tool contains a footprint viewer. Clicking the image:images/icons/icon_footprint_browser_24.png[footprint viewer icon] button in the top toolbar launches the footprint viewer and shows the selected footprint.

image::images/zh/footprint_view.png[scaledwidth="90%", alt="查看封装"]

The top toolbar contains the following commands:

[width="90%", cols="10%,90%"]
|=======================================================================
|image:images/icons/refresh_24.png[]
|Refresh view
|image:images/icons/zoom_in_24.png[]
|Zoom in

|image:images/icons/zoom_out_24.png[]
|Zoom out

|image:images/icons/zoom_fit_in_page_24.png[]
|Zoom to fit drawing in display area

|image:images/icons/shape_3d_24.png[]
|Show 3D viewer
|=======================================================================

The left toolbar contains the following commands:

[width="90%", cols="10%,90%"]
|=======================================================================
|image:images/icons/cursor_24.png[]
|Use the select tool

|image:images/icons/measurement_24.png[]
|Interactively measure between two points

|image:images/icons/grid_24.png[]
|Display grid dots or lines

|image:images/icons/polar_coord_24.png[]
|Switch between polar and cartesian coordinate systems

|image:images/icons/unit_inch_24.png[]
|Use inches

|image:images/icons/unit_mil_24.png[]
|Display coordinates in mils (1/1000 of an inch)

|image:images/icons/unit_mm_24.png[]
|Display coordinates in millimeters

|image:images/icons/cursor_shape_24.png[]
|Toggle display of full-window crosshairs

|image:images/icons/pad_number_24.png[]
|Toggle between drawing pads in sketch or normal mode

|image:images/icons/pad_sketch_24.png[]
|Toggle between drawing pads in normal mode or outline mode

|image:images/icons/text_sketch_24.png[]
|Toggle between drawing text in normal mode or outline mode

|image:images/icons/show_mod_edge_24.png[]
|Toggle between drawing graphic lines in normal mode or outline mode
|=======================================================================

===== 查看当前 3D 模型
Clicking the image:images/icons/shape_3d_24.png[3D Viewer icon] button opens the footprint in the 3D model viewer.

NOTE: If a 3D model does not exist for the current footprint, only the footprint itself will be shown in the 3D Viewer.

image::images/zh/3d_window.png[scaledwidth="90%", alt="3D 模型查看"]

The 3D Viewer is described in the xref:../pcbnew/pcbnew_inspecting.adoc#threed-viewer[PCB Editor manual].


:experimental:

[[erc]]
== 使用电气规则检查进行设计验证

=== 简介

The Electrical Rules Check (ERC) tool performs an automatic check of your schematic. The ERC checks for any errors in your sheet, such as unconnected pins, unconnected hierarchical symbols, shorted outputs, etc. ERC output is reported as errors or warnings depending on the severity of the issue detected.

Naturally, an automatic check is not infallible, and it is not possible to detect all design errors. Such a check is still very useful, because it allows you to detect many oversights and small errors. All detected issues should be checked and addressed before proceeding.

The quality of the ERC is directly related to the care taken in declaring electrical pin properties during symbol library creation.

image::images/zh/dialog_erc.png[alt="ERC 对话框", scaledwidth="70%"]

[[how-to-use-erc]]
=== 如何使用 ERC

ERC can be started by clicking on the icon image:images/icons/erc_24.png[ERC icon].

在原理图元素上设置警告, 以引发 ERC 错误 (引脚或标签)。

[NOTE]
====
* 在此对话框窗口中，单击错误消息时，您可以跳转到原理图中的相应标记。
* 在原理图中，右键单击标记以访问相应的诊断消息。
====

You can also delete error markers from the dialog and set specific ERC messages to be suppressed by using the right-click context menu.

image::images/erc_ignore_warning.png[alt="Ignore ERC warning", scaledwidth="70%"]

[[example-of-erc]]
=== ERC 的示例

image::images/erc_pointers.png[alt="ERC 指针", scaledwidth="70%"]

在这里, 您可以看到四个错误:

* 两个输出错误地连接在一起（红色箭头）。
* 两个输入未连接（绿色箭头）。
* 隐藏电源端口出现错误，缺少电源标志（顶部为绿色箭头）。

[[displaying-diagnostics]]
=== 显示诊断

通过右键单击标记，弹出菜单允许您访问 ERC 标记诊断窗口。

image::images/zh/erc_pointers_info.png[alt="ERC 指针信息", scaledwidth="70%"]

当单击标记错误信息时，您可以获得错误的描述。

image::images/erc_pointers_message.png[alt="ERC pointers message", scaledwidth="80%"]

[[power-pins-and-power-flags]]
=== 电源引脚和电源标志

It is common to have an error or a warning on power pins, as shown in the example above, even though all seems normal. This happens in designs where the power is provided through connectors or other components that are not marked as power sources (unlike a regulator output, which is represented by a Power Out pin). Therefore ERC won't detect any Power Out pin connected to the net and will determine it is not driven by a power source.

To avoid this warning, connect the net to `PWR_FLAG` symbol on such a power net as shown in the following example. The `PWR_FLAG` symbol is found in the `power` symbol library. Alternatively, connect any power output pin to the net; `PWR_FLAG` is simply a symbol with a single power output pin.

image::images/eeschema_power_pins_and_flags.png[alt="Power pins and flags", scaledwidth="70%"]

然后错误标记将消失。

Ground nets often need a `PWR_FLAG` as well, because voltage regulators have outputs declared as power outputs, but their ground pins are typically marked as power inputs. Therefore grounds can appear unconnected to a source unless a `PWR_FLAG` symbol is used.

[[configuration]]
=== 配置

The _Pin Conflicts Map_ panel in Schematic Setup allows you to configure connectivity rules to define electrical conditions for errors and warnings based on what types of pins are connected to each other

image::images/eeschema_erc_options.png[alt="Schematic ERC Pin Conflicts Map", scaledwidth="70%"]

单击所需的单元格方块可以更改规则，使其循环选择：正常，警告，错误。

image::images/eeschema_erc_severity.png[alt="Schematic ERC severity settings", scaledwidth="70%"]
The _Violation Severity_ panel in Schematic Setup lets you configure what types of ERC messages should be reported as Errors, Warnings or ignored.

[[erc-report-file]]
=== ERC 报告文件

通过选中写入 ERC 报告选项，可以生成并保存 ERC 报告文件。 ERC 报告文件的文件扩展名为 .erc。 以下是 ERC 报告文件的示例。

----------------------------------------------------------------------
ERC control (4/1/1997-14:16:4)

***** Sheet 1 (INTERFACE UNIVERSAL)
ERC: Warning Pin input Unconnected @ 8.450, 2.350
ERC: Warning passive Pin Unconnected @ 8.450, 1.950
ERC: Warning: BiDir Pin connected to power Pin (Net 6) @ 10.100, 3.300
ERC: Warning: Power Pin connected to BiDir Pin (Net 6) @ 4.950, 1.400

>> Errors ERC: 4
----------------------------------------------------------------------

:experimental:

[[schematic-to-pcb]]
== Transfer Schematic to PCB

=== 概述
Use the Update PCB from Schematic tool to sync design information from the Schematic Editor to the Board Editor. The tool can be accessed with **Tools** -> **Update PCB from Schematic** (kbd:[F8]) in both the schematic and board editors. You can also use the image:images/icons/update_pcb_from_sch_24.png[Update PCB from Schematic icon] icon in the top toolbar of the Board Editor.

NOTE: Update PCB from Schematic is the preferred way to transfer design information from the schematic to the PCB. In older versions of KiCad, the equivalent process was to export a netlist from the Schematic Editor and import it into the Board Editor. It is no longer necessary to use a netlist file.

image::images/update_pcb_from_schematic.png[alt="Update PCB from schematic", scaledwidth="70%"]

The tool adds the footprint for each symbol to the board and transfers updated schematic information to the board. In particular, the board's net connections are updated to match the schematic.

The changes that will be made to the PCB are listed in the _Changes To Be Applied_ pane. The PCB is not modified until you click the **Update PCB** button.

You can show or hide different types of messages using the checkboxes at the bottom of the window. A report of the changes can be saved to a file using the **Save...** button.

=== Options

The tool has several options to control its behavior.

[cols="1,2"]
|===
| Option | Description

| Re-link footprints to schematic symbols based on their reference designators
| Footprints are normally linked to schematic symbols via a unique identifier
created when the symbol is added to the schematic. A symbol's unique identifier
cannot be changed.

If checked, each footprint in the PCB will be re-linked to the symbol that has
the same reference designator as the footprint.

If unchecked, footprints and symbols will be linked by unique identifier as
usual, rather than by reference designator. Each footprint's reference
designator will be updated to match the reference designator of its linked
symbol.

This option should generally be left unchecked. It is useful for specific
workflows that rely on changing the links between schematic symbols and
footprints, such as refactoring a schematic for easier layout or replicating
layout between identical channels of a design.

| Delete footprints with no symbols
| If checked, any footprint in the PCB without a corresponding symbol in the
schematic will be deleted from the PCB. Footprints with the "Not in schematic"
attribute will be unaffected.

If unchecked, footprints without a corresponding symbol will not be deleted.

| Replace footprints with those specified in the schematic
| If checked, footprints in the PCB will be replaced with the footprint that is
specified in the corresponding schematic symbol.

If unchecked, footprints that are already in the PCB will not be changed, even
if the schematic symbol is updated to specify a different footprint.
|===

:experimental:

[[plot-and-print]]
== 绘图和打印

=== 简介

您可以通过文件菜单访问打印和绘图命令。

image::images/eeschema_file_menu_plot.png[alt="eeschema_file_menu_plot_png", scaledwidth="60%"]

The supported output formats are Postscript, PDF, SVG, DXF and HPGL. You can also directly print to your printer.

[[common-printing-commands]]
=== 常见的打印命令

绘制当前页面:: 仅打印当前工作表的一个文件。

绘制所有页面:: 允许您绘制整个层次结构（为每个工作表生成一个打印文件）。

[[plot-in-postscript]]
=== 在 Postscript 中绘制

此命令允许您创建 PostScript 文件。

image::images/eeschema_plot_postscript.png[alt="eeschema_plot_postscript_png", scaledwidth="70%"]

文件名是扩展名为 .ps 的工作表名称。 您可以禁用 ”绘制边框和标题栏“ 选项。 如果要创建用于封装的 postscript 文件（格式 .eps），这通常用于在文字处理软件中插入图表，这非常有用。 消息窗口显示创建的文件名。

[[plot-in-pdf]]
=== 以 PDF 格式绘制

image::images/eeschema_plot_pdf.png[alt="eeschema_plot_pdf.png", scaledwidth="70%"]

允许您使用 PDF 格式创建打印文件。 文件名是扩展名为 .pdf 的工作表名称。

[[plot-in-svg]]
=== 在 SVG 中绘图

image::images/eeschema_plot_svg.png[alt="eeschema_plot_svg_png", scaledwidth="70%"]

允许您使用矢量格式 SVG 创建打印文件。 文件名是扩展名为 .svg 的工作表名称。

[[plot-in-dxf]]
=== 在 DXF 中绘图

image::images/eeschema_plot_dxf.png[alt="eeschema_plot_dxf_png", scaledwidth="70%"]

允许您使用 DXF 格式创建打印文件。 文件名是扩展名为 .dxf 的工作表名称。

[[plot-in-hpgl]]
=== 在 HPGL 中绘图

此命令允许您创建 HPGL 文件。 在这种格式中，您可以定义：

* 页面大小。
* 原点。
* 笔宽（mm）。

绘图仪设置对话框窗口如下所示：

image::images/eeschema_plot_hpgl.png[alt="eeschema_plot_hpgl_png", scaledwidth="70%"]

输出文件名将是工作表名称加上扩展名 .plt。

[[sheet-size-selection]]
==== 纸张尺寸选择

通常检查纸张尺寸。 在这种情况下，将使用标题栏菜单中定义的纸张尺寸，并且所选的比例将为1.如果选择了不同的纸张尺寸（A4 为 A0，或 A 为 E），则自动调整比例以填充页面。

[[offset-adjustments]]
==== 偏移调整

对于所有标准尺寸，您可以调整偏移以尽可能准确地使图形居中。 由于绘图仪在工作表的中心或左下角有原点，因此必须能够引入偏移以便正确绘图。

一般来说：

* 对于原点位于纸张中心的绘图仪，偏移量必须为负值并设置为纸张尺寸的一半。
* 对于原点位于纸张左下角的绘图仪，偏移量必须设置为0。

要设置偏移量：

* 选择纸张尺寸。
* 设置偏移量 X 和偏移量 Y.
* 单击接受偏移量。

[[print-on-paper]]
=== 在纸上打印

This command, available via the icon image:images/icons/print_button_24.png[Print icon], allows you to visualize and generate design files for the standard printer.

image::images/print_dialog.png[alt="print_dialog_png", scaledwidth="50%"]

“打印表格参考和标题栏” 选项可启用或禁用图纸参考和标题栏。

“黑白打印” 选项设置单色打印。 如果使用黑白激光打印机，通常需要此选项，因为颜色打印成半色调，通常不太可读。

:experimental:

[[symbol-editor]]
== Symbol Editor

[[general-information-about-symbol-libraries]]
=== 关于符号库的一般信息

A symbol is a schematic element which contains a graphical representation, electrical connections, and text fields describing the symbol. Symbols used in a schematic are stored in symbol libraries. KiCad provides a symbol editing tool that allows you to create libraries, add, delete or transfer symbols between libraries, export symbols to files, and import symbols from files. The symbol editing tool provides a simple way to manage symbols and symbol libraries.

[[symbol-library-overview]]
=== 符号库概述

符号库由一个或多个符号组成。 通常，符号按功能，类型和/或制造商进行逻辑分组。

符号由以下部分组成：

* Graphical items (lines, circles, arcs, text, etc.) that determine how symbol looks in a schematic.
* Pins which have both graphic properties (line, clock, inverted, low level active, etc.) and electrical properties (input, output, bidirectional, etc.) used by the Electrical Rules Check (ERC) tool.
* 诸如参考，值，PCB设计的相应封装名称等字段等。

Symbols can be derived from another symbol in the same library. Derived symbols share the base symbol's graphical shape and pin definitions, but can override the base symbol's property fields (value, footprint, footprint filters, datasheet, description, etc.). Derived symbols can be used to define symbols that are similar to a base part. For example, 74LS00, 74HC00, and 7437 symbols could all be derived from a 7400 symbol. In previous versions of KiCad, derived symbols were referred to as aliases.

正确的符号设计需要：

* 定义符号是否由一个或多个单元组成。
* Defining if the symbol has an alternate body style (also known as a De Morgan representation).
* 使用线条，矩形，圆形，多边形和文本设计其符号表示。
* 通过仔细定义每个引脚的图形元素，名称，编号和电气属性（输入，输出，三态，电源端口等）来添加引脚。
* Determining if the symbol should be derived from another symbol with the same graphical design and pin definition.
* 添加可选字段，例如 PCB 设计软件使用的封装名称和/或定义其可见性。
* 通过添加描述字符串和数据表链接等来记录符号。
* 将其保存在所需的库中。

[[symbol-library-editor-overview]]
=== 符号库编辑器概述

符号库编辑器主窗口如下所示。 它由三个工具栏组成，可快速访问常用功能和符号查看/编辑区域。 并非所有命令都可在工具栏上使用，但可以使用菜单访问。

image::images/libedit_main_window.png[alt="Symbol Editor main window", scaledwidth="95%"]

[[main-toolbar]]
==== 主工具栏

The main tool bar is located at the top of the main window. It consists of the undo/redo commands, zoom commands, symbol properties dialogs, and unit/representation management controls.

image::images/toolbar_libedit.png[alt="Symbol Editor toolbar", scaledwidth="95%"]

[width="100%", cols="20%,80%"]
|=======================================================================
|image:images/icons/new_component_24.png[New symbol icon]
|Create a new symbol in the selected library.

|image:images/icons/save_24.png[Save icon]
|Save the currently selected library. All modified symbols in the library will
be saved.

|image:images/icons/undo_24.png[Undo icon]
|Undo last edit.

|image:images/icons/redo_24.png[Redo icon]
|Redo last undo.

|image:images/icons/refresh_24.png[Refresh icon]|Refresh display.

|image:images/icons/zoom_in_24.png[Zoom in icon]|Zoom in.

|image:images/icons/zoom_out_24.png[Zoom out icon]|Zoom out.

|image:images/icons/zoom_fit_in_page_24.png[Zoom to fit page icon]|Zoom to fit symbol in display.

|image:images/icons/zoom_selection_24.png[Zoom to selection icon]|Zoom to fit selection.

|image:images/icons/rotate_ccw_24.png[Rotate counterclockwise icon]|Rotate counter-clockwise.

|image:images/icons/rotate_cw_24.png[Rotate clockwise icon]|Rotate clockwise.

|image:images/icons/mirror_h_24.png[Mirror horizontally icon]|Mirror horizontally.

|image:images/icons/mirror_v_24.png[Mirror vertically icon]|Mirror vertically.

|image:images/icons/part_properties_24.png[Symbol properties icon]
|Edit the current symbol properties.

|image:images/icons/pin_table_24.png[Pin table icon]
|Edit the symbol's pins in a tablular interface.

|image:images/icons/datasheet_24.png[Datasheet icon]
|Open the symbol's datasheet. The button will be disabled if no datasheet is
defined for the current symbol.

|image:images/icons/erc_24.png[ERC icon]
|Test the current symbol for design errors.

|image:images/icons/morgan1_24.png[Normal body style icon]
|Select the normal body style. The button is disabled if the current
symbol does not have an alternate body style.

|image:images/icons/morgan2_24.png[Alternate body style icon]
|Select the alternate body style. The button is disabled if the current
symbol does not have an alternate body style.

|image:images/toolbar_libedit_part.png[alt="Unit dropdown",width="80%"]
|Select the unit to display. The drop down control will be disabled if
the current symbol is not derived from a symbol with multiple units.

|image:images/icons/pin2pin_24.png[Synchronized pin edit mode icon]
|Enable synchronized pins edit mode. When this mode is enabled, any pin
modifications are propagated to all other symbol units. Pin number changes are
not propagated. This mode is automatically enabled for symbols with multiple
interchangeable units and cannot be enabled for symbols with only one unit.

|image:images/icons/add_symbol_to_schematic_24.png[Add symbol to schematic icon]
Insert current symbol into schematic.

|=======================================================================

[[element-toolbar]]
==== 元素工具栏

The vertical toolbar located on the right hand side of the main window allows you to place all of the elements required to design a symbol.

[width="100%", cols="10%,90%"]
|=======================================================================
|image:images/icons/cursor_24.png[Cursor icon]
|Select tool. Right-clicking with the select tool opens the context menu
for the object under the cursor. Left-clicking with the select tool
displays the attributes of the object under the cursor in the message
panel at the bottom of the main window. Double-left-clicking with the
select tool will open the properties dialog for the object under the
cursor.

|image:images/icons/pin_24.png[Pin icon]
|Pin tool. Left-click to add a new pin.

|image:images/icons/text_24.png[Text icon]
|Graphical text tool. Left-click to add a new graphical text item.

|image:images/icons/add_rectangle_24.png[Add rectangle icon]
|Rectangle tool. Left-click to begin drawing the first corner of a
graphical rectangle. Left-click again to place the opposite corner of
the rectangle.

|image:images/icons/add_circle_24.png[Add circle icon]
|Circle tool. Left-click to begin drawing a new graphical circle from
the center. Left-click again to define the radius of the circle.

|image:images/icons/add_arc_24.png[Add arc icon]
|Arc tool. Left-click to begin drawing a new graphical arc item from the
first arc end point. Left-click again to define the second arc end point.
Adjust the radius by dragging the arc center point.

|image:images/icons/add_line_24.png[Add line icon]
|Connected line tool. Left-click to begin drawing a new graphical line item
in the current symbol. Left-click for each additional connected line.
Double-left-click to complete the line.

|image:images/icons/anchor_24.png[Anchor icon]
|Anchor tool. Left-click to set the anchor position of the symbol.

|image:images/icons/delete_cursor_24.png[Delete icon]
|Delete tool. Left-click to delete an object from the current symbol.
|=======================================================================

[[options-toolbar]]
==== 选项工具栏

The vertical tool bar located on the left hand side of the main window allows you to set some of the editor drawing options.

[width="100%", cols="10%,90%"]
|=======================================================================
|image:images/icons/grid_24.png[Grid icon]
|Toggle grid visibility on and off.

|image:images/icons/unit_inch_24.png[Inch unit icon]
|Set units to inches.

|image:images/icons/unit_mil_24.png[Millimeter unit icon]
|Set units to mils (0.001 inch).

|image:images/icons/unit_mm_24.png[Millimeter unit icon]
|Set units to millimeters.

|image:images/icons/cursor_shape_24.png[Cursor shape icon]
|Toggle full screen cursor on and off.

|image:images/icons/pin_show_etype_24.png[Show pintype icon]
|Toggle display of pin electrical types.

|image:images/icons/search_tree_24.png[Symbol tree icon]
|Toggle display of libraries and symbols.
|=======================================================================

[[library-selection-and-maintenance]]
=== 库选择与维护

The selection of the current library is possible via the image:images/icons/search_tree_24.png[Symbol tree icon] icon which shows you all available libraries and allows you to select one. When a symbol is loaded or saved, it will be put in this library. The library name of a symbol is the contents of its `Value` field.

[[select-and-save-a-symbol]]
==== 选择并保存符号

[[symbol-selection]]
===== 符号选择

Clicking the image:images/icons/search_tree_24.png[Symbol tree icon] icon on the left tool bar toggles the treeview of libraries and symbols. Clicking on a symbol opens that symbol.

[NOTE]
Some symbols are derived from other symbols. Derived symbol names are displayed in __italics__ in the treeview. If a derived symbol is opened, its symbol graphics will not be editable. Its symbol fields will be editable as normal. To edit the graphics of a base symbol and all of its derived symbols, open the base symbol.

[[save-a-symbol]]
===== 保存符号

After modification, a symbol can be saved in the current library or a different library.

To save the modified symbol in the current library, click the image:images/icons/save_24.png[Save icon] icon. The modifications will be written to the existing symbol.

NOTE: Saving a modified symbol also saves all other modified symbols in the same library.

To save the symbol changes to a new symbol, click **File** -> **Save As...**. The symbol can be saved in the current library or a different library. A new name can be set for the symbol.

To create a new file containing only the current symbol, click **File** -> **Export** -> **Symbol...**. This file will be a standard library file which will contain only one symbol.

[[creating-library-symbols]]
=== 创建库符号

[[create-a-new-symbol]]
==== 创建一个新符号

A new symbol can be created by clicking the image:images/icons/new_component_24.png[New symbol icon] icon. You will be asked for a number of symbol properties.

* A symbol name (this name is used as the default value for the `Value` field in the schematic editor)
* An optional base symbol to derive the new symbol from. The new symbol will use the base symbol's graphical shape and pin configuration, but other symbol information can be modified in the derived symbol. The base symbol must be in the same library as the new derived symbol.
* The reference designator prefix (`U`, `C`, `R`...).
* The number of units per package, and whether those units are interchangeable (for example a 7400 is made of 4 units per package).
* If an alternate body style (sometimes referred to as a "De Morgan equivalent") is desired.
* Whether the symbol is a power symbol. Power symbols appear in the "Add Power Port" dialog in the Schematic editor, their `Value` fields are not editable in the schematic, they cannot be assigned a footprint and they are not added to the PCB, and they are not included in the bill of materials.
* Whether the symbol should be excluded from the bill of materials.
* Whether the symbol should be excluded from the PCB.

There are also several graphical options.

* The offset between the end of each pin and its pin name.
* Whether the pin number and pin name should be displayed.
* Whether the pin names should be displayed alongside the pins or at the ends of the pins inside the symbol body.

These properties can also be changed later in the <<symbol-properties, Symbol Properties window>>.

image::images/eeschema_new_symbol_properties.png[alt="New symbol properties", scaledwidth="50%"]

将使用上面的属性创建一个新符号，它将出现在编辑器中，如下所示。

image::images/eeschema_libedit_new.png[alt="Newly created symbol", scaledwidth="95%"]

The blue cross in the center is the symbol anchor, which specifies the symbol origin i.e. the coordinates (0, 0). The anchor can be repositioned by selecting the image:images/icons/anchor_24.png[Anchor icon] icon and clicking on the new desired anchor position.

[[create-a-symbol-from-another-symbol]]
==== 从另一个符号创建符号

通常，您要制作的符号类似于符号库中已有的符号。 在这种情况下，很容易加载和修改现有符号。

* 加载将用作起点的符号。
* Save a new copy of the symbol using **File** -> **Save As...**. The Save As dialog will prompt for a name for the new symbol and the library to save it in.
* 根据需要编辑新符号。
* Save the modified symbol.

[[symbol-properties]]
==== 符号属性

Symbol properties are set when the symbol is created but they can be modified at any point. To change the symbol properties, click on the image:images/icons/part_properties_24.png[Symbol properties icon] icon to show the dialog below.

image::images/eeschema_properties_for_symbol.png[alt="符号属性", scaledwidth="60%"]

It is important to correctly set the number of units per package and the alternate symbolic representation, if enabled, because when pins are edited or created the corresponding pins for each unit will be affected. If you change the number of units per package after pin creation and editing, there will be additional work to specify the pins and graphics for the new unit. Nevertheless, it is possible to modify these properties at any time.

The graphic options "Show pin number" and "Show pin name" define the visibility of the pin number and pin name text. The option "Place pin names inside" defines the pin name position relative to the pin body. The pin names will be displayed inside the symbol outline if the option is checked. In this case the "Pin Name Position Offset" property defines the shift of the text away from the body end of the pin. A value from 0.02 to 0.05 inches is usually reasonable.

下面的示例显示了未选中 “放置引脚名称” 选项的符号。 注意名称和引脚号的位置。

image::images/eeschema_uncheck_pin_name_inside.png[alt="Place pin name inside unchecked", scaledwidth="95%"]

[[symbol-name-description-and-keywords]]
===== Symbol Name, Description, and Keywords

The symbol's name is the same as the `Value` field. When the symbol name is changed the value also changes, and vice versa. The symbol's name in the library also changes accordingly.

The symbol description should contain a brief description of the component, such as the component function, distinguishing features, and package options. The keywords should contain additional terms related to the component. Keywords are used primarily to assist in searching for the symbol.

image::images/eeschema_add_symbol_search_description.png[alt="Searching for a symbol in the add a symbol dialog", scaledwidth="65%"]

A symbol's name, description, and keywords are all used when searching for symbols in the Symbol Editor and Add a Symbol dialog. The description and keywords are displayed in the Symbol Library Browser and Add a Symbol dialog.

[[footprint-filters]]
===== Footprint Filters

The footprint filters tab is used to define which footprints are appropriate to use with the symbol. The filters can be applied in the Footprint Assignment tool so that only appropriate footprints are displayed for each symbol.

Multiple footprint filters can be defined. Footprints that match any of the filters will be displayed; if no filters are defined, then all footprints will be displayed.

Filters can use wildcards: `\*` matches any number of characters, including zero, and `?` matches zero or one characters. For example, `SOIC-*` would match the `SOIC-8_3.9x4.9mm_P1.27mm` footprint as well as any other footprint beginning with `SOIC-`. The filter `SOT?23` matches `SOT23` as well as `SOT-23`.

image::images/eeschema_libedit_footprint.png[alt="Footprint filters", scaledwidth="70%"]

[[symbols-with-alternate-symbolic-representation]]
==== 带有替代符号表示的符号

If the symbol has an alternate body style defined, one body style must be selected for editing at a time. To edit the normal representation, click the image:images/icons/morgan1_24.png[Normal representation icon] icon.

To edit the alternate representation, click on the image:images/icons/morgan2_24.png[Alternate representation icon] icon. Use the image:images/toolbar_libedit_alias.png[images/toolbar_libedit_part.png] dropdown shown below to select the unit you wish to edit.

image::images/eeschema_libedit_select_unit.png[alt="Selecting a symbol unit", scaledwidth="80%"]

[[graphical-elements]]
=== 图形元素

Graphical elements create the visual representation of a symbol and contain no electrical connection information. Graphical elements are created with the following tools:

* 由起点和终点定义的线和多边形。
* 由两个对角线定义的矩形。
* 由中心和半径定义的圆。
* 由弧的起点和终点及其中心定义的弧。 弧度从0°到180°。

主窗口右侧的垂直工具栏允许您放置设计符号表示所需的所有图形元素。

[[graphical-element-membership]]
==== 图形元素成员资格

每个图形元素（线，弧，圆等）可以被定义为对于所有单元和/或主体样式是共同的或者对于给定单元和/或主体样式是特定的。 右键单击元素可以快速访问元素选项，以显示所选元素的上下文菜单。 下面是线元素的上下文菜单。

image::images/eeschema_libedit_context_menu.png[alt="Graphic line context menu", scaledwidth="80%"]

您还可以双击元素以修改其属性。 下面是多边形元素的属性对话框。

image::images/eeschema_libedit_polyline_properties.png[alt="Graphic line properties", scaledwidth="50%"]

图形元素的属性是:

* "Line width" defines the width of the element's line in the current drawing units.
* "Fill Style" determines if the shape defined by the graphical element is to be drawn unfilled, background filled, or foreground filled.
* "Common to all units in symbol" determines if the graphical element is drawn for each unit in symbol with more than one unit per package or if the graphical element is only drawn for the current unit.
* "Common to all body styles (De Morgan)" determines if the graphical element is drawn for each symbolic representation in symbols with an alternate body style or if the graphical element is only drawn for the current body style.

[[graphical-text-elements]]
==== 图形文本元素

The image:images/icons/text_24.png[Text icon] icon allows for the creation of graphical text. Graphical text is automatically oriented to be readable, even when the symbol is mirrored. Please note that graphical text items are not the same as symbol fields.

[[multiple-units-per-symbol-and-alternate-body-styles]]
=== 每个符号多个单位和替代体型样式

Symbols can have up to two body styles (a standard symbol and an alternate symbol often referred to as a "De Morgan equivalent") and/or have more than one unit per package (logic gates for example). Some symbols can have more than one unit per package each with different symbols and pin configurations.

Consider for instance a relay with two switches, which can be designed as a symbol with three different units: a coil, switch 1, and switch 2. Designing a symbol with multiple units per package and/or alternate body styles is very flexible. A pin or a body symbol item can be common to all units or specific to a given unit or they can be common to both symbolic representation so are specific to a given symbol representation.

By default, pins are specific to a unit and body style. When a pin is common to all units or all body styles, it only needs to be created once. This is also the case for the body style graphic shapes and text, which may be common to each unit, but typically are specific to each body style).

[[example-of-a-symbol-with-multiple-noninterchangeable-units]]
==== Example of a Symbol With Multiple Noninterchangeable Units

For an example of a symbol with multiple units that are not interchangeable, consider a relay with 3 units per package: a coil, switch 1, and switch 2.

The three units are not all the same, so "All units are interchangeable" should be deselected in the Symbol Properties dialog. Alternatively, this option could have been specified when the symbol was initially created.

image::images/eeschema_libedit_not_interchangeable.png[alt="Uncheck all units are interchangeable", scaledwidth="60%"]

===== Unit A

image::images/eeschema_libedit_unit1.png[alt="Relay unit A", scaledwidth="45%"]

===== Unit B

image::images/eeschema_libedit_unit2.png[alt="Relay unit B", scaledwidth="45%"]

===== Unit C

image::images/eeschema_libedit_unit3.png[alt="Relay unit C", scaledwidth="45%"]

Unit A does not have the same symbol and pin layout as Units B and C, so the units are not interchangeable.

NOTE: "Synchronized Pins Edit Mode" can be enabled by clicking the image:images/icons/pin2pin_24.png[Synchronized pins edit mode icon] icon. In this mode, pin modifications are propagated between symbol units; changes made in one unit will be reflected in the other units as well. When this mode is disabled, pin changes made in one unit do not affect other units. This mode is enabled automatically when "All units are interchangeable" is checked, but it can be disabled. The mode cannot be enabled when "All units are interchangeable" is unchecked or when the symbol only has one unit.

[[graphical-symbolic-elements]]
===== 图形符号元素

Shown below are properties for a graphic body element. In the relay example above, the three units have different symbolic representations. Therefore, each unit was created separately and the graphical body elements have the "Common to all units in symbol" setting disabled.

image::images/eeschema_libedit_disable_common.png[alt="Disable common to all units in symbol", scaledwidth="70%"]

[[pin-creation-and-editing]]
=== 引脚创建和编辑

You can click on the image:images/icons/pin_24.png[Pin icon] icon to create and insert a pin. The editing of all pin properties is done by double-clicking on the pin or right-clicking on the pin to open the pin context menu. Pins must be created carefully, because any error will have consequences on the PCB design. Any pin already placed can be edited, deleted, and/or moved.

[[pin-overview]]
==== 引笔概述

A pin is defined by its graphical representation, its name and its number. The pin's name and number can contain letters, numbers, and symbols, but not spaces. For the Electrical Rules Check (ERC) tool to be useful, the pin's electrical type (input, output, tri-state...) must also be defined correctly. If this type is not defined properly, the schematic ERC check results may be invalid.

重要笔记：

* Symbol pins are matched to footprint pads by number. The pin number in the symbol must match the corresponding pad number in the footprint.
* Do not use spaces in pin names and numbers. Spaces will be automatically replaced with underscores (`_`).
* To define a pin name with an inverted signal (overline) use the `~` (tilde) character followed by the text to invert in braces. For example `~{FO}O` would display [overline]#FO# O.
* If the pin name is empty, the pin is considered unnamed.
* Pin names can be repeated in a symbol.
* Pin numbers must be unique in a symbol.

[[pin-properties]]
==== 引脚属性

image::images/eeschema_libedit_pin_properties.png[alt="Pin properties", scaledwidth="95%"]

引脚属性对话框允许您编辑引脚的所有特性。 创建引脚或双击现有引脚时，会自动弹出此对话框。 此对话框允许您修改：

* The pin name and text size.
* The pin number and text size.
* The pin length.
* The pin electrical type and graphical style.
* 单位和替代代表成员资格。
* Pin visibility.
* <<alternate-pin-definitions,Alternate pin definitions>>.

[[pin-graphic-styles]]
==== Pin Graphic Styles

Shown in the figure below are the different pin graphic styles. The choice of graphic style does not have any influence on the pin's electrical type.

image::images/eeschema_libedit_pin_properties_style.png[alt="Pin graphic styles", scaledwidth="95%"]

[[pin-electrical-types]]
==== 引脚电气类型

Choosing the correct electrical type is important for the schematic ERC tool. ERC will check that pins are connected appropriately, for example ensuring that input pins are driven and power inputs receive power from an appropriate source.

[width="100%", cols="25%,75%"]
|=======================================================================
| Pin Type | Description
| Input | A pin which is exclusively an input.
| Output | A pin which is exclusively an output.
| Bidirectional | A pin that can be either an input or an output, such as a
microcontroller data bus pin.
| Tri-state | A three state output pin (high, low, or high impedance)
| Passive | A passive symbol pin: resistors, connectors, etc.
| Free | A pin that can be freely connected to any other pin without electrical
concerns.
| Unspecified | A pin for which the ERC check does not matter.
| Power input | A symbol's power pin. As a special case, power input pins that
are marked invisible are automatically connected to the net with the same name.
See the <<creating-power-ports, Power Ports section>> for more information.
| Power output | A pin that provides power to other pins, such as a regulator
output.
| Open collector | An open collector logic output.
| Open emitter | An open emitter logic output.
| Unconnected | A pin that should not be connected to anything.
|=======================================================================

[[pushing-pin-properties-to-other-pins]]
==== Pushing Pin Properties to Other Pins

You can apply the length, name size, or number size of a pin to the other pins in the symbol by right clicking the pin and selecting **Push Pin Length**, **Push Pin Name Size**, or **Push Pin Number Size**, respectively.

image::images/eeschema_libedit_pin_context_menu.png[alt="Pin context menu", scaledwidth="60%"]

[[defining-pins-for-multiple-units-and-alternate-symbolic-representations]]
==== 为多个单元和备用符号表示定义引脚

Symbols with multiple units and/or graphical representations are particularly problematic when creating and editing pins. The majority of pins are specific to each symbol unit (because each unit has a different set of pins) and to each body style (because the form and position is different between the normal body style and the alternate form).

The symbol library editor allows the simultaneous creation of pins. By default, changes made to a pin are made for all units of a multiple unit symbol and to both representations for symbols with an alternate symbolic representation. The only exception to this is the pin's graphical type and name, which remain unlinked between symbol units and body styles. This dependency was established to allow for easier pin creation and editing in most cases. This dependency can be disabled by toggling the image:images/icons/pin2pin_24.png[Synchronized pin edit mode icon] icon on the main tool bar. This will allow you to create pins for each unit and representation completely independently.

Pins can be common or specific to different units. Pins can also be common to both symbolic representations or specific to each symbolic representation. When a pin is common to all units, it only has to drawn once. Pins are set as common or specific in the pin properties dialog.

An example is the output pin in the 7400 quad dual input NAND gate. Since there are four units and two symbolic representations, there are eight separate output pins defined in the symbol definition. When creating a new 7400 symbol, unit A of the normal symbolic representation will be shown in the library editor. To edit the pin style in the alternate symbolic representation, it must first be enabled by clicking the image:images/icons/morgan2_24.png[Alternate representation icon] button on the tool bar. To edit the pin number for each unit, select the appropriate unit using the image:images/toolbar_libedit_alias.png[images/toolbar_libedit_alias.png] drop down control.

[[pin-table]]
==== Pin Table

Another way to edit pins is to use the Pin Table, which is accessible via the image:images/icons/pin_table_24.png[Pin table icon] icon. The Pin Table displays all of the pins in the symbol and their properties in a table view, so it is useful for making bulk pin changes.

Any pin property can be edited by clicking on the appropriate cell. Pins can be added and removed with the image:images/icons/small_plus_16.png[Plus icon] and image:images/icons/small_trash_16.png[Trash icon] icons, respectively.

NOTE: Columns of the pin table can be shown or hidden by right-clicking on the header row and checking or unchecking additional columns. Some columns are hidden by default.

The screenshot below shows the pin table for a quad opamp.

image::images/eeschema_libedit_pin_table.png[alt="Pin table", scaledwidth="95%"]

[[alternate-pin-definitions]]
==== Alternate Pin Definitions

Pins can have alternate pin definitions added to them. Alternate pin definitions allow a user to select a different name, electrical type, and graphical style for a pin when the symbol has been placed in the schematic. This can be used for pins that have multiple functions, such as microcontroller pins.

Alternate pin definitions are added in the Pin Properties dialog as shown below. Each alternate definition contains a pin name, electrical type, and graphic style. This microcontroller pin has all of its peripheral functions defined in the symbol as alternate pin names.

image::images/eeschema_libedit_alternate_pin_definitions.png[alt="Alternate pin definitions", scaledwidth="60%"]

Alternate pin definitions are selected in the Schematic Editor once the symbol has been placed in the schematic. The alternate pin is assigned in the Alternate Pin Assignments tab of the Symbol Properties dialog. Alternate definitions are selectable in the dropdown in the Alternate Assignment column.

image::images/eeschema_alternate_pin_assignment_selection.png[alt="Selecting an alternate pin definition", scaledwidth="60%"]

[[symbol-fields]]
=== 符号字段

All library symbols are defined with four default fields. The reference designator, value, footprint assignment, and datasheet link fields are created whenever a symbol is created or copied. Only the reference designator and value fields are required.

Symbols defined in libraries are typically defined with only these four default fields. Additional fields such as vendor, part number, unit cost, etc. can be added to library symbols but generally this is done in the schematic editor so the additional fields can be applied to all of the symbols in the schematic.

NOTE: A convenient way to create additional empty symbol fields is to use define field name templates. Field name templates define empty fields that are added to each symbol when it is inserted into the schematic. Field name templates can be defined globally (for all schematics) in the Schematic Editor Preferences, or they can be defined locally (specific to each project) in the Schematic Setup dialog.

[[editing-symbol-fields]]
==== 编辑符号字段

要编辑现有符号字段，请右键单击字段文本以显示下面显示的字段上下文菜单。

image::images/eeschema_libedit_field_context_menu.png[alt="Symbol field context menu", scaledwidth="35%"]

To add new fields, delete optional fields, or edit existing fields, use the image:images/icons/part_properties_24.png[Component properties icon] icon on the main tool bar to open the <<symbol-properties,Symbol Properties dialog>>.

Fields are text information associated a the symbol. Do not confuse them with text in the graphic representation of a symbol.

重要笔记：

* Modifying the `Value` field changes the name of the symbol. The symbol's name in the library will change when the symbol is saved.
* The Symbol Properties dialog must be used to edit a field that is empty or has the invisible attribute enabled because such fields cannot be clicked on.
* The footprint is defined as an absolute footprint using the `LIBNAME:FOOTPRINTNAME` format where `LIBNAME` is the name of the footprint library defined in the footprint library table (see the "Footprint Library Table" section in the PCB Editor manual) and `FOOTPRINTNAME` is the name of the footprint in the library `LIBNAME`.

[[creating-power-ports]]
=== Power Ports

Power ports, or power symbols, are conventionally used to label a wire as part of a power net, like `VCC`, `+5V`, or `GND`. In the schematic below, the `+3.3V` and `GND` symbols are power ports. In addition to acting as a visual indicator that a net is a power rail, a power port will determine the name of the net it is attached to. This is true even if there is another net label attached to the net; the net name determined by the power symbol overrides any other net names.

image::images/eeschema_power_port_example.png[alt="Power port example", scaledwidth="60%"]

It may be useful to place power symbols in a dedicated library. KiCad's symbol library places power symbols in the `power` library, and users may create libraries to store their own power symbols. If the "Define as power symbol" box is checked in a symbol's properties, that symbol will appear in the Schematic Editor's "Add Power Port" dialog for convenient access.

Power symbols are handled and created the same way as normal symbols, but there are several additional considerations described below. They consist of a graphical symbol and a pin of the type "Power input" that is marked hidden.

Below is an example of a `GND` power symbol.

image::images/eeschema_libedit_power_symbol.png[alt="Editing a power symbol", scaledwidth="95%"]

==== Creating a Power Port Symbol

Power Port symbols consist of a pin of type "Power input" that is marked invisible. Invisible power input pins have a special property of automatically connecting to a net with the same name as the pin name. A net that is wired to an invisible power input pin will therefore be named after the pin, even if there are other net labels on the net. This connection is global.

NOTE: If the power symbol has the "Define as power symbol" property checked, the power input pin does not need to be marked invisible. However, the convention is to make these pins invisible anyway.

image::images/eeschema_libedit_power_symbol_pin.png[alt="Power symbol pin", scaledwidth="60%"]

要创建电源符号, 请使用以下步骤:

* Add a pin of type "Power input", with "Visible" unchecked, and the pin named according to the desired net. Make the pin number `1`, the length `0`, and set the graphic style to "Line". The pin name establishes the connection to the net; in this case the pin will automatically connect to the net `GND`. The pin number, length, and line style do not matter electrically.
* Place the pin on the symbol anchor.
* Use the shape tools to draw the symbol graphics.
* Set the symbol value. The symbol value does not matter electrically, but it is displayed in the schematic. To eliminate confusion, it should match the pin name (which determines the connected net name).
* Check the "Define as power symbol" box in Symbol Properties window. This makes the symbol appear in the "Add Power Port" dialog, makes the `Value` field read-only in the schematic, prevents the symbol from being assigned a footprint, and excludes the symbol from the board, BOM, and netlists.
* Set the symbol reference and uncheck the "Show" box. The reference text is not important except for the first character, which should be `\#`. For the power port shown above, the reference could be `#GND`. Symbols with references that begin with `#` are not added to the PCB, are not included in Bill of Materials exports or netlists, and they cannot be assigned a footprint in the footprint assignment tool. If a power port's reference does not begin with `#`, the character will be inserted automatically when the annotation or footprint assignment tools are run.

An easier method to create a new power port symbol is to use another symbol as a starting point, <<creating-a-symbol-from-another-symbol,as described earlier>>.

NOTE: When modifying an existing power port symbol, make sure to rename the pin name so that the new symbol connects to the appropriate power net.

:experimental:

[[viewlib]]
== 符号库浏览器

=== 简介

The Symbol Library Browser allows you to quickly examine the content of symbol libraries. The Symbol Library Viewer can be accessed by clicking image:images/icons/library_browser_24.png[Library viewer icon] icon on the main toolbar, **View** -> **Symbol Library Browser...**, or clicking **Select With Browser** in the "Choose Symbol" window.

image::images/eeschema_viewlib_choose.png[alt="eeschema_viewlib_choose_png", scaledwidth="60%"]

[[viewlib---main-screen]]
=== 视图-主屏幕

image::images/eeschema_viewlib_select_library.png[alt="eeschema_viewlib_select_library_png", scaledwidth="95%"]

要检查库的内容，请从左侧窗格的列表中选择一个库。 所选库中的所有符号都将显示在第二个窗格中。 选择符号名称以查看符号。

image::images/eeschema_viewlib_select_component.png[alt="eeschema_viewlib_select_component_png", scaledwidth="95%"]

[[viewlib-top-toolbar]]
=== 符号库浏览器顶部工具栏

符号库浏览器中的顶部工具栏如下所示。

image::images/toolbar_viewlib.png[alt="images/toolbar_viewlib.png", scaledwidth="95%"]

可用的命令是：

[width="100%", cols="20%,80%"]
|=======================================================================
|image:images/icons/library_browser_24.png[Symbol selection icon]
|Selection of the symbol which can be also selected in the displayed
list.

|image:images/icons/lib_previous_24.png[Previous symbol icon]
|Display previous symbol.

|image:images/icons/lib_next_24.png[Next symbol icon]
|Display next symbol.

|image:images/icons/refresh_24.png[] image:images/icons/zoom_in_24.png[]
image:images/icons/zoom_out_24.png[] image:images/icons/zoom_fit_in_page_24.png[]
|Zoom tools.

|image:images/icons/morgan1_24.png[] image:images/icons/morgan2_24.png[]
|Selection of the representation (normal or alternate) if an alternate
representation exists.

|image:images/toolbar_viewlib_part.png[alt="images/toolbar_viewlib_part.png",width="70%"]
|Selection of the unit for symbols that contain multiple units.

|image:images/icons/datasheet_24.png[icons/datasheet_png]
|If they exist, display the associated documents.

|image:images/icons/add_symbol_to_schematic_24.png[Add symbol to schematic icon]
|Close the browser and place the selected symbol in the schematic.
|=======================================================================

:experimental:

[[create-a-netlist]]
== 创建网络列表

=== 概述

A netlist is a file which describes electrical connections between symbol pins. These connections are referred to as nets. Netlist files contain:

* A list of symbols and their pins.
* A list of connections (nets) between symbol pins.

Many different netlist formats exist. Sometimes the symbols list and the list of nets are two separate files. This netlist is fundamental in the use of schematic capture software, because the netlist is the link with other electronic CAD software, such as:

* PCB 布局软件。
* 原理图和电信号模拟器。
* Programmable logic (FPGA, CPLD, etc.) compilers.

KiCad supports several netlist formats:

* KiCad format, which can be imported by the KiCad PCB Editor. However, the <<eeschema_schematic_to_pcb.adoc#schematic-to-pcb,"Update PCB from Schematic">> tool should be used instead of importing a KiCad netlist into the PCB editor.
* OrCAD PCB2 format, for designing PCBs with OrCAD.
* CADSTAR format, for designing PCBs with CADSTAR.
* Spice format, for use with various external circuit simulators.

NOTE: In KiCad version 5.0 and later, it is not necessary to create a netlist for transferring a design from the schematic editor to the PCB editor. Instead, use the <<eeschema_schematic_to_pcb.adoc#schematic-to-pcb,"Update PCB from Schematic">> tool.

[[netlist-formats]]
=== 网表格式

Netlists are exported with the Export Netlist dialog (**File**->**Export**->**Netlist...**).

Several netlist formats are available, and are selectable with the tabs at the top of the window. Some netlist formats have options.

Clicking the **Export Netlist** button prompts for a netlist filename and saves the netlist.

[NOTE]
Netlist generation can take up to several minutes for large schematics.

Custom generators can be added by clicking the **Add Generator...** button. Custom generators are external tools that are called by KiCad, for example Python scripts or XSLT stylesheets. For more information on custom netlist generators, see <<adding-new-netlist-generators,the section on adding custom netlist generators>>.

==== KiCad Netlist Format

image::images/eeschema_netlist_dialog_kicad.png[alt="KiCad netlist export", scaledwidth="70%"]

The KiCad netlist exporter does not have any options.

NOTE: In KiCad version 5.0 and later, it is not necessary to create a netlist for transferring a design from the schematic editor to the PCB editor. Instead, use the <<eeschema_schematic_to_pcb.adoc#schematic-to-pcb,"Update PCB from Schematic">> tool.

==== OrCAD PCB2 Netlist Format

image::images/eeschema_netlist_dialog_orcad.png[alt="OrCAD netlist export", scaledwidth="70%"]

The OrCAD netlist exporter does not have any options.

==== CADSTAR Netlist Format

image::images/eeschema_netlist_dialog_cadstar.png[alt="CADSTAR netlist export", scaledwidth="70%"]

The CADSTAR netlist exporter does not have any options.

==== Spice Netlist Format

image::images/eeschema_netlist_dialog_spice.png[alt="Spice netlist export", scaledwidth="70%"]

The Spice netlist format offers several options.

When the *Reformat passive symbol values* box is checked, passive symbol values will be adjusted to be compatible with Spice. Specifically:

* `&mu;` and `M` as unit prefixes are replaced with `u` and `Meg`, respectively
* Units are removed (e.g. `4.7k&ohm;` is changed to `4.7k`)
* Values in RKM format are rewritten to be Spice-compatible (e.g. `4u7` is changed to `4.7u`)

The Spice netlist exporter also provides an easy way to simulate the generated netlist with an external simulator. This can be useful for running a simulation without using <<eeschema_simulator.adoc#simulator,KiCad's internal ngspice simulator>>, or for running an ngspice simulation with options that are not supported by KiCad's simulator tool.

Enter the path to the external simulator in the text box, with `%I` representing the generated netlist. Click the **Create Netlist and Run Simulator Command** button to generate the netlist and automatically run the simulator.

NOTE: The default simulator command (`spice "%I"`) must be adjusted to point to a simulator installed on your system.

For more information on the contents of Spice netlists, see the <<spice-netlists,Spice netlist section>>.

[[netlist-examples]]
=== 网表示例

Below is the schematic from the `sallen_key` project included in KiCad's simulation demos.

image::images/eeschema_netlist_schematic.png[alt="sallen_key demo schematic", scaledwidth="95%"]

The KiCad format netlist for this schematic is as follows:

----
(export (version "E")
  (design
    (source "/usr/share/kicad/demos/simulation/sallen_key/sallen_key.kicad_sch")
    (date "Sun 01 May 2022 03:14:05 PM EDT")
    (tool "Eeschema (6.0.4)")
    (sheet (number "1") (name "/") (tstamps "/")
      (title_block
        (title)
        (company)
        (rev)
        (date)
        (source "sallen_key.kicad_sch")
        (comment (number "1") (value ""))
        (comment (number "2") (value ""))
        (comment (number "3") (value ""))
        (comment (number "4") (value ""))
        (comment (number "5") (value ""))
        (comment (number "6") (value ""))
        (comment (number "7") (value ""))
        (comment (number "8") (value ""))
        (comment (number "9") (value "")))))
  (components
    (comp (ref "C1")
      (value "100n")
      (libsource (lib "sallen_key_schlib") (part "C") (description ""))
      (property (name "Sheetname") (value ""))
      (property (name "Sheetfile") (value "sallen_key.kicad_sch"))
      (sheetpath (names "/") (tstamps "/"))
      (tstamps "00000000-0000-0000-0000-00005789077d"))
    (comp (ref "C2")
      (value "100n")
      (fields
        (field (name "Fieldname") "Value")
        (field (name "SpiceMapping") "1 2")
        (field (name "Spice_Primitive") "C"))
      (libsource (lib "sallen_key_schlib") (part "C") (description ""))
      (property (name "Fieldname") (value "Value"))
      (property (name "Spice_Primitive") (value "C"))
      (property (name "SpiceMapping") (value "1 2"))
      (property (name "Sheetname") (value ""))
      (property (name "Sheetfile") (value "sallen_key.kicad_sch"))
      (sheetpath (names "/") (tstamps "/"))
      (tstamps "00000000-0000-0000-0000-00005789085b"))
    (comp (ref "R1")
      (value "1k")
      (fields
        (field (name "Fieldname") "Value")
        (field (name "SpiceMapping") "1 2")
        (field (name "Spice_Primitive") "R"))
      (libsource (lib "sallen_key_schlib") (part "R") (description ""))
      (property (name "Fieldname") (value "Value"))
      (property (name "SpiceMapping") (value "1 2"))
      (property (name "Spice_Primitive") (value "R"))
      (property (name "Sheetname") (value ""))
      (property (name "Sheetfile") (value "sallen_key.kicad_sch"))
      (sheetpath (names "/") (tstamps "/"))
      (tstamps "00000000-0000-0000-0000-0000578906ff"))
    (comp (ref "R2")
      (value "1k")
      (fields
        (field (name "Fieldname") "Value")
        (field (name "SpiceMapping") "1 2")
        (field (name "Spice_Primitive") "R"))
      (libsource (lib "sallen_key_schlib") (part "R") (description ""))
      (property (name "Fieldname") (value "Value"))
      (property (name "SpiceMapping") (value "1 2"))
      (property (name "Spice_Primitive") (value "R"))
      (property (name "Sheetname") (value ""))
      (property (name "Sheetfile") (value "sallen_key.kicad_sch"))
      (sheetpath (names "/") (tstamps "/"))
      (tstamps "00000000-0000-0000-0000-000057890691"))
    (comp (ref "U1")
      (value "AD8051")
      (fields
        (field (name "Spice_Lib_File") "ad8051.lib")
        (field (name "Spice_Model") "AD8051")
        (field (name "Spice_Netlist_Enabled") "Y")
        (field (name "Spice_Primitive") "X"))
      (libsource (lib "sallen_key_schlib") (part "Generic_Opamp") (description ""))
      (property (name "Spice_Primitive") (value "X"))
      (property (name "Spice_Model") (value "AD8051"))
      (property (name "Spice_Lib_File") (value "ad8051.lib"))
      (property (name "Spice_Netlist_Enabled") (value "Y"))
      (property (name "Sheetname") (value ""))
      (property (name "Sheetfile") (value "sallen_key.kicad_sch"))
      (sheetpath (names "/") (tstamps "/"))
      (tstamps "00000000-0000-0000-0000-00005788ff9f"))
    (comp (ref "V1")
      (value "AC 1")
      (libsource (lib "sallen_key_schlib") (part "VSOURCE") (description ""))
      (property (name "Sheetname") (value ""))
      (property (name "Sheetfile") (value "sallen_key.kicad_sch"))
      (sheetpath (names "/") (tstamps "/"))
      (tstamps "00000000-0000-0000-0000-000057336052"))
    (comp (ref "V2")
      (value "DC 10")
      (fields
        (field (name "Fieldname") "Value")
        (field (name "Spice_Node_Sequence") "1 2")
        (field (name "Spice_Primitive") "V"))
      (libsource (lib "sallen_key_schlib") (part "VSOURCE") (description ""))
      (property (name "Fieldname") (value "Value"))
      (property (name "Spice_Primitive") (value "V"))
      (property (name "Spice_Node_Sequence") (value "1 2"))
      (property (name "Sheetname") (value ""))
      (property (name "Sheetfile") (value "sallen_key.kicad_sch"))
      (sheetpath (names "/") (tstamps "/"))
      (tstamps "00000000-0000-0000-0000-0000578900ba"))
    (comp (ref "V3")
      (value "DC 10")
      (fields
        (field (name "Fieldname") "Value")
        (field (name "Spice_Node_Sequence") "1 2")
        (field (name "Spice_Primitive") "V"))
      (libsource (lib "sallen_key_schlib") (part "VSOURCE") (description ""))
      (property (name "Fieldname") (value "Value"))
      (property (name "Spice_Primitive") (value "V"))
      (property (name "Spice_Node_Sequence") (value "1 2"))
      (property (name "Sheetname") (value ""))
      (property (name "Sheetfile") (value "sallen_key.kicad_sch"))
      (sheetpath (names "/") (tstamps "/"))
      (tstamps "00000000-0000-0000-0000-000057890232")))
  (libparts
    (libpart (lib "sallen_key_schlib") (part "C")
      (footprints
        (fp "C?")
        (fp "C_????_*")
        (fp "C_????")
        (fp "SMD*_c")
        (fp "Capacitor*"))
      (fields
        (field (name "Reference") "C")
        (field (name "Value") "C"))
      (pins
        (pin (num "1") (name "") (type "passive"))
        (pin (num "2") (name "") (type "passive"))))
    (libpart (lib "sallen_key_schlib") (part "Generic_Opamp")
      (fields
        (field (name "Reference") "U")
        (field (name "Value") "Generic_Opamp"))
      (pins
        (pin (num "1") (name "+") (type "input"))
        (pin (num "2") (name "-") (type "input"))
        (pin (num "3") (name "V+") (type "power_in"))
        (pin (num "4") (name "V-") (type "power_in"))
        (pin (num "5") (name "") (type "output"))))
    (libpart (lib "sallen_key_schlib") (part "R")
      (footprints
        (fp "R_*")
        (fp "Resistor_*"))
      (fields
        (field (name "Reference") "R")
        (field (name "Value") "R"))
      (pins
        (pin (num "1") (name "") (type "passive"))
        (pin (num "2") (name "") (type "passive"))))
    (libpart (lib "sallen_key_schlib") (part "VSOURCE")
      (fields
        (field (name "Reference") "V")
        (field (name "Value") "VSOURCE")
        (field (name "Fieldname") "Value")
        (field (name "Spice_Primitive") "V")
        (field (name "Spice_Node_Sequence") "1 2"))
      (pins
        (pin (num "1") (name "") (type "input"))
        (pin (num "2") (name "") (type "input")))))
  (libraries
    (library (logical "sallen_key_schlib")
      (uri "/usr/share/kicad/demos/simulation/sallen_key/sallen_key_schlib.kicad_sym")))
  (nets
    (net (code "1") (name "/lowpass")
      (node (ref "C1") (pin "1") (pintype "passive"))
      (node (ref "U1") (pin "2") (pinfunction "-") (pintype "input"))
      (node (ref "U1") (pin "5") (pintype "output")))
    (net (code "2") (name "GND")
      (node (ref "C2") (pin "2") (pintype "passive"))
      (node (ref "V1") (pin "2") (pintype "input"))
      (node (ref "V2") (pin "2") (pintype "input"))
      (node (ref "V3") (pin "1") (pintype "input")))
    (net (code "3") (name "Net-(C1-Pad2)")
      (node (ref "C1") (pin "2") (pintype "passive"))
      (node (ref "R1") (pin "1") (pintype "passive"))
      (node (ref "R2") (pin "2") (pintype "passive")))
    (net (code "4") (name "Net-(C2-Pad1)")
      (node (ref "C2") (pin "1") (pintype "passive"))
      (node (ref "R2") (pin "1") (pintype "passive"))
      (node (ref "U1") (pin "1") (pinfunction "+") (pintype "input")))
    (net (code "5") (name "Net-(R1-Pad2)")
      (node (ref "R1") (pin "2") (pintype "passive"))
      (node (ref "V1") (pin "1") (pintype "input")))
    (net (code "6") (name "VDD")
      (node (ref "U1") (pin "3") (pinfunction "V+") (pintype "power_in"))
      (node (ref "V2") (pin "1") (pintype "input")))
    (net (code "7") (name "VSS")
      (node (ref "U1") (pin "4") (pinfunction "V-") (pintype "power_in"))
      (node (ref "V3") (pin "2") (pintype "input")))))
----

In Spice format, the netlist is as follows:

----
.title KiCad schematic
.include "ad8051.lib"
XU1 Net-_C2-Pad1_ /lowpass VDD VSS /lowpass AD8051
C2 Net-_C2-Pad1_ GND 100n
C1 /lowpass Net-_C1-Pad2_ 100n
R2 Net-_C2-Pad1_ Net-_C1-Pad2_ 1k
R1 Net-_C1-Pad2_ Net-_R1-Pad2_ 1k
V1 Net-_R1-Pad2_ GND AC 1
V2 VDD GND DC 10
V3 GND VSS DC 10
.ac dec 10 1 1Meg
.end
----


[[notes-on-netlists]]
=== 关于网表的说明

[[netlist-name-precautions]]
==== 网表名称注意事项

Many software tools that use netlists do not accept spaces in component names, pins, nets, or other fields. Avoid using spaces in pins, labels, names, and value fields of components to ensure maximum compatibility.

In the same way, special characters other than letters and numbers can cause problems. Note that this limitation is not related to KiCad, but to the netlist formats that can then become untranslatable by other software that reads those netlist files.

[[spice-netlists]]
==== Spice netlists

Spice simulators expect simulation commands (`.PROBE`, `.AC`, `.TRAN`, etc.) to be included in the netlist.

Any text line included in the schematic diagram starting with a period (`.`) will be included in the netlist. If a text object contains multiple lines, only the lines beginning with a period will be included.

`.include` directives for including model library files are automatically added to the netlist based on the Spice model settings for the symbols in the schematic.

[[other-formats]]
=== 其他格式

KiCad supports custom netlist generators for exporting netlists in other formats. Some examples of netlist generators are given in the <<eeschema_creating_customized_netlists_and_bom_files.adoc#creating-customized-netlists-and-bom-files,custom netlist generators section>>.

A netlist generator is a script or program that converts the intermediate netlist file created by KiCad into the desired netlist format. The intermediate netlist file contains all of the netlist information required to create an arbitrary netlist for the schematic. Python and XSLT are commonly used tools to create custom netlist generators.

[[adding-new-netlist-generators]]
==== Adding new netlist generators

New netlist generators are added by clicking the **Add Generator...** button.

image::images/eeschema_netlist_dialog_add_plugin.png[alt="Custom Netlist Generator", scaledwidth="40%"]

New generators require a name and a command. The name is shown in the tab label, and the command is run whenever the **Export Netlist** button is clicked.

When the netlist is generated, KiCad creates an intermediate XML file which contains all of the netlist information from the schematic. The generator command is then run in order to transform the intermediate netlist into the desired netlist format.

The netlist command must be set up properly so that the netlist generator script takes the intermediate netlist file as input and outputs the desired netlist file. The `%I` argument represents the input intermediate netlist filename and the `%O` argument represents the output netlist filename. The exact netlist command will depend on the generator script used.

[[command-line-format]]
==== 命令行格式

Consider the following example which uses `xsltproc` to generate a netlist in PADS ASC format. `xsltproc` converts the intermediate netlist using the `netlist_form_pads-pcb.asc.xsl` stylesheet to define the output format:

`xsltproc -o %O.net /usr/share/kicad/plugins/netlist_form_pads-pcb.asc.xsl %I`

The purpose of each part of the command is as follows:

[width="100%", cols="58%,42%"]
|=======================================================================
|`xsltproc` |A tool to convert an XML file (the intermediate netlist) according
to an XSLT stylesheet.

|`-o %O.net` |Output filename. `%O` is replaced with the name of the
intermediate netlist file, which is `<schematic name>.xml`. Therefore in this
example the complete output filename is `<schematic name>.xml.net`. An arbitrary
output filename can be specified if desired with `-o <filename>`.

|`/usr/share/kicad/plugins/netlist_form_pads-pcb.asc.xsl` |XSLT stylesheet which
determines how the output is formatted. This particular stylesheet is included
with KiCad, but custom stylesheets can also be created.

|`%I` |Input (intermediate netlist) filename. `%I` is replaced with the name of
the intermediate netlist file, which is `<schematic name>.xml`.
|=======================================================================

For netlist generators that do not use `xsltproc`, the generator command will differ.

[[intermediate-netlist-file-format]]
==== 中间网表文件格式

See the <<eeschema_creating_customized_netlists_and_bom_files.adoc#creating-customized-netlists-and-bom-files,custom netlist generators section>> for more information about netlist generators, a description of the intermediate netlist format, and some examples of netlist generators.

:experimental:

[[creating-customized-netlists-and-bom-files]]
== 创建自定义网表和 BOM 文件

[[intermediate-netlist-file]]
=== 中间网表文件格式

BOM files and netlist files can be converted from an Intermediate netlist file created by KiCad.

此文件使用 XML 语法，称为中间网表。中间网表包含有关您的电路板的大量数据，因此，它可以与后处理一起用于创建 BOM 或其他报告。

根据输出（BOM 或网表），将在后处理中使用完整的中间网表文件的不同子集。

[[schematic-sample]]
==== 原理图样本

image::images/schematic-sample.png[alt="原理图样本", scaledwidth="95%"]

[[the-intermediate-netlist-file-sample]]
==== 中间网表文件示例

上述电路的相应中间网表 (使用 XML 语法) 如下所示。

-----------------------------------------------------------------
<?xml version="1.0" encoding="utf-8"?>
<export version="D">
  <design>
    <source>F:\kicad_aux\netlist_test\netlist_test.sch</source>
    <date>29/08/2010 20:35:21</date>
    <tool>eeschema (2010-08-28 BZR 2458)-unstable</tool>
  </design>
  <components>
    <comp ref="P1">
      <value>CONN_4</value>
      <libsource lib="conn" part="CONN_4"/>
      <sheetpath names="/" tstamps="/"/>
      <tstamp>4C6E2141</tstamp>
    </comp>
    <comp ref="U2">
      <value>74LS74</value>
      <libsource lib="74xx" part="74LS74"/>
      <sheetpath names="/" tstamps="/"/>
      <tstamp>4C6E20BA</tstamp>
    </comp>
    <comp ref="U1">
      <value>74LS04</value>
      <libsource lib="74xx" part="74LS04"/>
      <sheetpath names="/" tstamps="/"/>
      <tstamp>4C6E20A6</tstamp>
    </comp>
    <comp ref="C1">
      <value>CP</value>
      <libsource lib="device" part="CP"/>
      <sheetpath names="/" tstamps="/"/>
      <tstamp>4C6E2094</tstamp>
    </comp>
    <comp ref="R1">
      <value>R</value>
      <libsource lib="device" part="R"/>
      <sheetpath names="/" tstamps="/"/>
      <tstamp>4C6E208A</tstamp>
    </comp>
  </components>
  <libparts>
    <libpart lib="device" part="C">
      <description>Condensateur non polarise</description>
      <footprints>
        <fp>SM*</fp>
        <fp>C?</fp>
        <fp>C1-1</fp>
      </footprints>
      <fields>
        <field name="Reference">C</field>
        <field name="Value">C</field>
      </fields>
      <pins>
        <pin num="1" name="~" type="passive"/>
        <pin num="2" name="~" type="passive"/>
      </pins>
    </libpart>
    <libpart lib="device" part="R">
      <description>Resistance</description>
      <footprints>
        <fp>R?</fp>
        <fp>SM0603</fp>
        <fp>SM0805</fp>
        <fp>R?-*</fp>
        <fp>SM1206</fp>
      </footprints>
      <fields>
        <field name="Reference">R</field>
        <field name="Value">R</field>
      </fields>
      <pins>
        <pin num="1" name="~" type="passive"/>
        <pin num="2" name="~" type="passive"/>
      </pins>
    </libpart>
    <libpart lib="conn" part="CONN_4">
      <description>Symbole general de connecteur</description>
      <fields>
        <field name="Reference">P</field>
        <field name="Value">CONN_4</field>
      </fields>
      <pins>
        <pin num="1" name="P1" type="passive"/>
        <pin num="2" name="P2" type="passive"/>
        <pin num="3" name="P3" type="passive"/>
        <pin num="4" name="P4" type="passive"/>
      </pins>
    </libpart>
    <libpart lib="74xx" part="74LS04">
      <description>Hex Inverseur</description>
      <fields>
        <field name="Reference">U</field>
        <field name="Value">74LS04</field>
      </fields>
      <pins>
        <pin num="1" name="~" type="input"/>
        <pin num="2" name="~" type="output"/>
        <pin num="3" name="~" type="input"/>
        <pin num="4" name="~" type="output"/>
        <pin num="5" name="~" type="input"/>
        <pin num="6" name="~" type="output"/>
        <pin num="7" name="GND" type="power_in"/>
        <pin num="8" name="~" type="output"/>
        <pin num="9" name="~" type="input"/>
        <pin num="10" name="~" type="output"/>
        <pin num="11" name="~" type="input"/>
        <pin num="12" name="~" type="output"/>
        <pin num="13" name="~" type="input"/>
        <pin num="14" name="VCC" type="power_in"/>
      </pins>
    </libpart>
    <libpart lib="74xx" part="74LS74">
      <description>Dual D FlipFlop, Set &amp; Reset</description>
      <docs>74xx/74hc_hct74.pdf</docs>
      <fields>
        <field name="Reference">U</field>
        <field name="Value">74LS74</field>
      </fields>
      <pins>
        <pin num="1" name="Cd" type="input"/>
        <pin num="2" name="D" type="input"/>
        <pin num="3" name="Cp" type="input"/>
        <pin num="4" name="Sd" type="input"/>
        <pin num="5" name="Q" type="output"/>
        <pin num="6" name="~Q" type="output"/>
        <pin num="7" name="GND" type="power_in"/>
        <pin num="8" name="~Q" type="output"/>
        <pin num="9" name="Q" type="output"/>
        <pin num="10" name="Sd" type="input"/>
        <pin num="11" name="Cp" type="input"/>
        <pin num="12" name="D" type="input"/>
        <pin num="13" name="Cd" type="input"/>
        <pin num="14" name="VCC" type="power_in"/>
      </pins>
    </libpart>
  </libparts>
  <libraries>
    <library logical="device">
      <uri>F:\kicad\share\library\device.lib</uri>
    </library>
    <library logical="conn">
      <uri>F:\kicad\share\library\conn.lib</uri>
    </library>
    <library logical="74xx">
      <uri>F:\kicad\share\library\74xx.lib</uri>
    </library>
  </libraries>
  <nets>
    <net code="1" name="GND">
      <node ref="U1" pin="7"/>
      <node ref="C1" pin="2"/>
      <node ref="U2" pin="7"/>
      <node ref="P1" pin="4"/>
    </net>
    <net code="2" name="VCC">
      <node ref="R1" pin="1"/>
      <node ref="U1" pin="14"/>
      <node ref="U2" pin="4"/>
      <node ref="U2" pin="1"/>
      <node ref="U2" pin="14"/>
      <node ref="P1" pin="1"/>
    </net>
    <net code="3" name="">
      <node ref="U2" pin="6"/>
    </net>
    <net code="4" name="">
      <node ref="U1" pin="2"/>
      <node ref="U2" pin="3"/>
    </net>
    <net code="5" name="/SIG_OUT">
      <node ref="P1" pin="2"/>
      <node ref="U2" pin="5"/>
      <node ref="U2" pin="2"/>
    </net>
    <net code="6" name="/CLOCK_IN">
      <node ref="R1" pin="2"/>
      <node ref="C1" pin="1"/>
      <node ref="U1" pin="1"/>
      <node ref="P1" pin="3"/>
    </net>
  </nets>
</export>
-----------------------------------------------------------------

[[conversion-to-a-new-netlist-format]]
=== 转换为新的网表格式

通过将后处理过滤器应用于中间网表文件，您可以生成外部网表文件以及 BOM 文件。 由于此转换是文本到文本转换，因此可以使用 Python，XSLT 或任何其他能够将 XML 作为输入的工具来编写此后处理过滤器。

XSLT itself is an XML language very suitable for XML transformations. There is a free program called _xsltproc_ that you can download and install. The xsltproc program can be used to read the Intermediate XML netlist input file, apply a style-sheet to transform the input, and save the results in an output file. Use of xsltproc requires a style-sheet file using XSLT conventions. The full conversion process is handled by KiCad, after it is configured once to run xsltproc in a specific way.

[[xslt-approach]]
=== XSLT 方法

描述 XSL 转换（XSLT）的文档可在此处获得：

*http://www.w3.org/TR/xslt*

[[create-a-pads-pcb-netlist-file]]
==== 创建 Pads-Pcb 网表文件

“pads-pcb” 的格式由两部分组成。

* 封装列表。

* 网表: 按网络对焊盘引用进行分组。

紧接下面是样式表，它将中间网表文件转换为 pad-pcb 网表格式：

-------------------------------------------------------------------------------
<?xml version="1.0" encoding="ISO-8859-1"?>
<!--XSL style sheet to Eeschema Generic Netlist Format to PADS netlist format
    Copyright (C) 2010, SoftPLC Corporation.
    GPL v2.

    如何使用:
        https://lists.launchpad.net/kicad-developers/msg05157.html
-->

<!DOCTYPE xsl:stylesheet [
  <!ENTITY nl  "&#xd;&#xa;"> <!--new line CR, LF -->
]>

<xsl:stylesheet version="1.0" xmlns:xsl="http://www.w3.org/1999/XSL/Transform">
<xsl:output method="text" omit-xml-declaration="yes" indent="no"/>

<xsl:template match="/export">
    <xsl:text>*PADS-PCB*&nl;*PART*&nl;</xsl:text>
    <xsl:apply-templates select="components/comp"/>
    <xsl:text>&nl;*NET*&nl;</xsl:text>
    <xsl:apply-templates select="nets/net"/>
    <xsl:text>*END*&nl;</xsl:text>
</xsl:template>

<!-- for each component -->
<xsl:template match="comp">
    <xsl:text> </xsl:text>
    <xsl:value-of select="@ref"/>
    <xsl:text> </xsl:text>
    <xsl:choose>
        <xsl:when test = "footprint != '' ">
            <xsl:apply-templates select="footprint"/>
        </xsl:when>
        <xsl:otherwise>
            <xsl:text>unknown</xsl:text>
        </xsl:otherwise>
    </xsl:choose>
    <xsl:text>&nl;</xsl:text>
</xsl:template>

<!-- for each net -->
<xsl:template match="net">
    <!-- nets are output only if there is more than one pin in net -->
    <xsl:if test="count(node)>1">
        <xsl:text>*SIGNAL* </xsl:text>
        <xsl:choose>
            <xsl:when test = "@name != '' ">
                <xsl:value-of select="@name"/>
            </xsl:when>
            <xsl:otherwise>
                <xsl:text>N-</xsl:text>
                <xsl:value-of select="@code"/>
            </xsl:otherwise>
        </xsl:choose>
        <xsl:text>&nl;</xsl:text>
        <xsl:apply-templates select="node"/>
    </xsl:if>
</xsl:template>

<!-- for each node -->
<xsl:template match="node">
    <xsl:text> </xsl:text>
    <xsl:value-of select="@ref"/>
    <xsl:text>.</xsl:text>
    <xsl:value-of select="@pin"/>
    <xsl:text>&nl;</xsl:text>
</xsl:template>

</xsl:stylesheet>
-------------------------------------------------------------------------------

这是运行 xsltproc 后的 pads-pcb 输出文件：

------------------
*PADS-PCB*
*PART*
P1 unknown
U2 unknown
U1 unknown
C1 unknown
R1 unknown
*NET*
*SIGNAL* GND
U1.7
C1.2
U2.7
P1.4
*SIGNAL* VCC
R1.1
U1.14
U2.4
U2.1
U2.14
P1.1
*SIGNAL* N-4
U1.2
U2.3
*SIGNAL* /SIG_OUT
P1.2
U2.5
U2.2
*SIGNAL* /CLOCK_IN
R1.2
C1.1
U1.1
P1.3

*END*
------------------

进行此转换的命令行是：

-------------------------------------------
kicad\\bin\\xsltproc.exe -o test.net kicad\\bin\\plugins\\netlist_form_pads-pcb.xsl test.tmp
-------------------------------------------

[[create-a-cadstar-netlist-file]]
==== 创建一个 Cadstar 网表文件

Cadstar 格式由两个部分组成。

* 封装列表。

* 网表: 按网络对焊盘引用进行分组。

以下是进行此特定转换的样式表文件：

-----
<?xml version="1.0" encoding="ISO-8859-1"?>
<!--XSL style sheet to Eeschema Generic Netlist Format to CADSTAR netlist format
    Copyright (C) 2010, Jean-Pierre Charras.
    Copyright (C) 2010, SoftPLC Corporation.
    GPL v2.

<!DOCTYPE xsl:stylesheet [
  <!ENTITY nl  "&#xd;&#xa;"> <!--new line CR, LF -->
]>

<xsl:stylesheet version="1.0" xmlns:xsl="http://www.w3.org/1999/XSL/Transform">
<xsl:output method="text" omit-xml-declaration="yes" indent="no"/>

<!-- Netlist header -->
<xsl:template match="/export">
    <xsl:text>.HEA&nl;</xsl:text>
    <xsl:apply-templates select="design/date"/>  <!-- Generate line .TIM <time> -->
    <xsl:apply-templates select="design/tool"/>  <!-- Generate line .APP <eeschema version> -->
    <xsl:apply-templates select="components/comp"/>  <!-- Generate list of components -->
    <xsl:text>&nl;&nl;</xsl:text>
    <xsl:apply-templates select="nets/net"/>          <!-- Generate list of nets and connections -->
    <xsl:text>&nl;.END&nl;</xsl:text>
</xsl:template>

 <!-- Generate line .TIM 20/08/2010 10:45:33 -->
<xsl:template match="tool">
    <xsl:text>.APP "</xsl:text>
    <xsl:apply-templates/>
    <xsl:text>"&nl;</xsl:text>
</xsl:template>

 <!-- Generate line .APP "eeschema (2010-08-17 BZR 2450)-unstable" -->
<xsl:template match="date">
    <xsl:text>.TIM </xsl:text>
    <xsl:apply-templates/>
    <xsl:text>&nl;</xsl:text>
</xsl:template>

<!-- for each component -->
<xsl:template match="comp">
    <xsl:text>.ADD_COM </xsl:text>
    <xsl:value-of select="@ref"/>
    <xsl:text> </xsl:text>
    <xsl:choose>
        <xsl:when test = "value != '' ">
            <xsl:text>"</xsl:text> <xsl:apply-templates select="value"/> <xsl:text>"</xsl:text>
        </xsl:when>
        <xsl:otherwise>
            <xsl:text>""</xsl:text>
        </xsl:otherwise>
    </xsl:choose>
    <xsl:text>&nl;</xsl:text>
</xsl:template>

<!-- for each net -->
<xsl:template match="net">
    <!-- nets are output only if there is more than one pin in net -->
    <xsl:if test="count(node)>1">
    <xsl:variable name="netname">
        <xsl:text>"</xsl:text>
        <xsl:choose>
            <xsl:when test = "@name != '' ">
                <xsl:value-of select="@name"/>
            </xsl:when>
            <xsl:otherwise>
                <xsl:text>N-</xsl:text>
                <xsl:value-of select="@code"/>
        </xsl:otherwise>
        </xsl:choose>
        <xsl:text>"&nl;</xsl:text>
        </xsl:variable>
        <xsl:apply-templates select="node" mode="first"/>
        <xsl:value-of select="$netname"/>
        <xsl:apply-templates select="node" mode="others"/>
    </xsl:if>
</xsl:template>

<!-- for each node -->
<xsl:template match="node" mode="first">
    <xsl:if test="position()=1">
       <xsl:text>.ADD_TER </xsl:text>
    <xsl:value-of select="@ref"/>
    <xsl:text>.</xsl:text>
    <xsl:value-of select="@pin"/>
    <xsl:text> </xsl:text>
    </xsl:if>
</xsl:template>

<xsl:template match="node" mode="others">
    <xsl:choose>
        <xsl:when test='position()=1'>
        </xsl:when>
        <xsl:when test='position()=2'>
           <xsl:text>.TER     </xsl:text>
        </xsl:when>
        <xsl:otherwise>
           <xsl:text>         </xsl:text>
        </xsl:otherwise>
    </xsl:choose>
    <xsl:if test="position()>1">
        <xsl:value-of select="@ref"/>
        <xsl:text>.</xsl:text>
        <xsl:value-of select="@pin"/>
        <xsl:text>&nl;</xsl:text>
    </xsl:if>
</xsl:template>

</xsl:stylesheet>
-----

这是 Cadstar 输出文件。

-----
.HEA
.TIM 21/08/2010 08:12:08
.APP "eeschema (2010-08-09 BZR 2439)-unstable"
.ADD_COM P1 "CONN_4"
.ADD_COM U2 "74LS74"
.ADD_COM U1 "74LS04"
.ADD_COM C1 "CP"
.ADD_COM R1 "R"


.ADD_TER U1.7 "GND"
.TER     C1.2
         U2.7
         P1.4
.ADD_TER R1.1 "VCC"
.TER     U1.14
         U2.4
         U2.1
         U2.14
         P1.1
.ADD_TER U1.2 "N-4"
.TER     U2.3
.ADD_TER P1.2 "/SIG_OUT"
.TER     U2.5
         U2.2
.ADD_TER R1.2 "/CLOCK_IN"
.TER     C1.1
         U1.1
         P1.3

.END
-----

[[create-a-orcadpcb2-netlist-file]]
==== 创建 OrcadPCB2 网表文件

此格式只有一个部分是封装列表。 每个封装包括其参考网络的焊盘列表。

以下是此特定转换的样式表：

-----
<?xml version="1.0" encoding="ISO-8859-1"?>
<!--XSL style sheet to Eeschema Generic Netlist Format to CADSTAR netlist format
    Copyright (C) 2010, SoftPLC Corporation.
    GPL v2.

    如何使用:
        https://lists.launchpad.net/kicad-developers/msg05157.html
-->

<!DOCTYPE xsl:stylesheet [
  <!ENTITY nl  "&#xd;&#xa;"> <!--new line CR, LF -->
]>

<xsl:stylesheet version="1.0" xmlns:xsl="http://www.w3.org/1999/XSL/Transform">
<xsl:output method="text" omit-xml-declaration="yes" indent="no"/>

<!--
    Netlist header
    Creates the entire netlist
    (can be seen as equivalent to main function in C
-->
<xsl:template match="/export">
    <xsl:text>( { Eeschema Netlist Version 1.1  </xsl:text>
    <!-- Generate line .TIM <time> -->
<xsl:apply-templates select="design/date"/>
<!-- Generate line eeschema version ... -->
<xsl:apply-templates select="design/tool"/>
<xsl:text>}&nl;</xsl:text>

<!-- Generate the list of components -->
<xsl:apply-templates select="components/comp"/>  <!-- Generate list of components -->

<!-- end of file -->
<xsl:text>)&nl;*&nl;</xsl:text>
</xsl:template>

<!--
    Generate id in header like "eeschema (2010-08-17 BZR 2450)-unstable"
-->
<xsl:template match="tool">
    <xsl:apply-templates/>
</xsl:template>

<!--
    Generate date in header like "20/08/2010 10:45:33"
-->
<xsl:template match="date">
    <xsl:apply-templates/>
    <xsl:text>&nl;</xsl:text>
</xsl:template>

<!--
    This template read each component
    (path = /export/components/comp)
    creates lines:
     ( 3EBF7DBD $noname U1 74LS125
      ... pin list ...
      )
    and calls "create_pin_list" template to build the pin list
-->
<xsl:template match="comp">
    <xsl:text> ( </xsl:text>
    <xsl:choose>
        <xsl:when test = "tstamp != '' ">
            <xsl:apply-templates select="tstamp"/>
        </xsl:when>
        <xsl:otherwise>
            <xsl:text>00000000</xsl:text>
        </xsl:otherwise>
    </xsl:choose>
    <xsl:text> </xsl:text>
    <xsl:choose>
        <xsl:when test = "footprint != '' ">
            <xsl:apply-templates select="footprint"/>
        </xsl:when>
        <xsl:otherwise>
            <xsl:text>$noname</xsl:text>
        </xsl:otherwise>
    </xsl:choose>
    <xsl:text> </xsl:text>
    <xsl:value-of select="@ref"/>
    <xsl:text> </xsl:text>
    <xsl:choose>
        <xsl:when test = "value != '' ">
            <xsl:apply-templates select="value"/>
        </xsl:when>
        <xsl:otherwise>
            <xsl:text>"~"</xsl:text>
        </xsl:otherwise>
    </xsl:choose>
    <xsl:text>&nl;</xsl:text>
    <xsl:call-template name="Search_pin_list" >
        <xsl:with-param name="cmplib_id" select="libsource/@part"/>
        <xsl:with-param name="cmp_ref" select="@ref"/>
    </xsl:call-template>
    <xsl:text> )&nl;</xsl:text>
</xsl:template>

<!--
    This template search for a given lib component description in list
    lib component descriptions are in /export/libparts,
    and each description start at ./libpart
    We search here for the list of pins of the given component
    This template has 2 parameters:
        "cmplib_id" (reference in libparts)
        "cmp_ref"   (schematic reference of the given component)
-->
<xsl:template name="Search_pin_list" >
    <xsl:param name="cmplib_id" select="0" />
    <xsl:param name="cmp_ref" select="0" />
        <xsl:for-each select="/export/libparts/libpart">
            <xsl:if test = "@part = $cmplib_id ">
                <xsl:apply-templates name="build_pin_list" select="pins/pin">
                    <xsl:with-param name="cmp_ref" select="$cmp_ref"/>
                </xsl:apply-templates>
            </xsl:if>
        </xsl:for-each>
</xsl:template>


<!--
    This template writes the pin list of a component
    from the pin list of the library description
    The pin list from library description is something like
          <pins>
            <pin num="1" type="passive"/>
            <pin num="2" type="passive"/>
          </pins>
    Output pin list is ( <pin num> <net name> )
    something like
            ( 1 VCC )
            ( 2 GND )
-->
<xsl:template name="build_pin_list" match="pin">
    <xsl:param name="cmp_ref" select="0" />

    <!-- write pin numner and separator -->
    <xsl:text>  ( </xsl:text>
    <xsl:value-of select="@num"/>
    <xsl:text> </xsl:text>

    <!-- search net name in nets section and write it: -->
    <xsl:variable name="pinNum" select="@num" />
    <xsl:for-each select="/export/nets/net">
        <!-- net name is output only if there is more than one pin in net
             else use "?" as net name, so count items in this net
        -->
        <xsl:variable name="pinCnt" select="count(node)" />
        <xsl:apply-templates name="Search_pin_netname" select="node">
            <xsl:with-param name="cmp_ref" select="$cmp_ref"/>
            <xsl:with-param name="pin_cnt_in_net" select="$pinCnt"/>
            <xsl:with-param name="pin_num"> <xsl:value-of select="$pinNum"/>
            </xsl:with-param>
        </xsl:apply-templates>
    </xsl:for-each>

    <!-- close line -->
    <xsl:text> )&nl;</xsl:text>
</xsl:template>

<!--
    This template writes the pin netname of a given pin of a given component
    from the nets list
    The nets list description is something like
      <nets>
        <net code="1" name="GND">
          <node ref="J1" pin="20"/>
              <node ref="C2" pin="2"/>
        </net>
        <net code="2" name="">
          <node ref="U2" pin="11"/>
        </net>
    </nets>
    This template has 2 parameters:
        "cmp_ref"   (schematic reference of the given component)
        "pin_num"   (pin number)
-->

<xsl:template name="Search_pin_netname" match="node">
    <xsl:param name="cmp_ref" select="0" />
    <xsl:param name="pin_num" select="0" />
    <xsl:param name="pin_cnt_in_net" select="0" />

    <xsl:if test = "@ref = $cmp_ref ">
        <xsl:if test = "@pin = $pin_num">
        <!-- net name is output only if there is more than one pin in net
             else use "?" as net name
        -->
            <xsl:if test = "$pin_cnt_in_net>1">
                <xsl:choose>
                    <!-- if a net has a name, use it,
                        else build a name from its net code
                    -->
                    <xsl:when test = "../@name != '' ">
                        <xsl:value-of select="../@name"/>
                    </xsl:when>
                    <xsl:otherwise>
                        <xsl:text>$N-0</xsl:text><xsl:value-of select="../@code"/>
                    </xsl:otherwise>
                </xsl:choose>
            </xsl:if>
            <xsl:if test = "$pin_cnt_in_net &lt;2">
                <xsl:text>?</xsl:text>
            </xsl:if>
        </xsl:if>
    </xsl:if>

</xsl:template>

</xsl:stylesheet>
-----

这是 OrcadPCB2 输出文件。

-----------------------------------------------------
( { Eeschema Netlist Version 1.1  29/08/2010 21:07:51
eeschema (2010-08-28 BZR 2458)-unstable}
 ( 4C6E2141 $noname P1 CONN_4
  (  1 VCC )
  (  2 /SIG_OUT )
  (  3 /CLOCK_IN )
  (  4 GND )
 )
 ( 4C6E20BA $noname U2 74LS74
  (  1 VCC )
  (  2 /SIG_OUT )
  (  3 N-04 )
  (  4 VCC )
  (  5 /SIG_OUT )
  (  6 ? )
  (  7 GND )
  (  14 VCC )
 )
 ( 4C6E20A6 $noname U1 74LS04
  (  1 /CLOCK_IN )
  (  2 N-04 )
  (  7 GND )
  (  14 VCC )
 )
 ( 4C6E2094 $noname C1 CP
  (  1 /CLOCK_IN )
  (  2 GND )
 )
 ( 4C6E208A $noname R1 R
  (  1 VCC )
  (  2 /CLOCK_IN )
 )
)
*
-----------------------------------------------------

[[eeschema-plugins-interface]]
==== Netlist plugins interface

Intermediate Netlist converters can be automatically launched within the Schematic Editor.

[[init-the-dialog-window-1]]
===== 初始化对话窗口

可以通过单击 添加插件 按钮添加新的网表插件用户界面选项卡。

image::images/eeschema_plugin_add_plugin.png[alt="eeschema_plugin_add_plugin_png", scaledwidth="50%"]

以下是 PadsPcb 选项卡的配置数据：

image::images/eeschema_plugin_padspcb.png[alt="eeschema_plugin_padspcb_png", scaledwidth="80%"]

[[plugin-configuration-parameters]]
===== 插件配置参数

The netlist plug-in configuration dialog requires the following information:

* 标题：例如，网表格式的名称。

* 用于启动转换器的命令行。

单击网表按钮后，将发生以下情况：

1.  KiCad creates an intermediate netlist file *.xml, for instance test.xml.

2.  KiCad runs the plug-in by reading test.xml and creates test.net.

[[generate-netlist-files-with-the-command-line]]
===== 使用命令行生成网络列表文件

假设我们使用程序 _xsltproc.exe_ 将工作表样式应用于中间文件，则使用以下命令执行 _xsltproc.exe_：

_xsltproc.exe -o <output filename> < style-sheet filename> <input XML file to convert>_

在 Windows 下的 KiCad 中，命令行如下：

_f:/kicad/bin/xsltproc.exe -o "%O" f:/kicad/bin/plugins/netlist_form_pads-pcb.xsl "%I"_

在 Linux 下，命令变为如下：

_xsltproc -o "%O" /usr/local/kicad/bin/plugins/netlist_form_pads-pcb.xsl "%I"_

Where _netlist_form_pads-pcb.xsl_ is the style-sheet that you are applying. Do not forget the double quotes around the file names, this allows them to have spaces after the substitution by KiCad.

命令行格式接受文件名的参数:

支持的格式设置参数是。

* %B => 基本文件名和所选输出文件的路径，减去路径和扩展名。

* %I => 完整的文件名和临时输入文件的路径（中间网络文件）。

* %O => 完整的文件名和用户选择的输出文件的路径。

_%I_ 将被实际的中间文件名替换

_%O_ 将替换为实际输出文件名。

[[command-line-format-example-for-xsltproc]]
===== 命令行格式：xsltproc 的示例

_xsltproc_ 的命令行格式如下：

<path of xsltproc> xsltproc <xsltproc parameters>

在 Windows 下：

*f:/kicad/bin/xsltproc.exe -o "%O" f:/kicad/bin/plugins/netlist_form_pads-pcb.xsl "%I"*

在 Linux 下：

*xsltproc -o "%O" /usr/local/kicad/bin/plugins/netlist_form_pads-pcb.xsl "%I"*

上面的示例假设 xsltproc 安装在 Windows 下的 PC 上，所有文件都位于 kicad/bin 中。

[[bill-of-materials-generation]]
==== 物料清单（BOM）生成

由于中间网表文件包含有关已使用元件的所有信息，因此可以从中提取 BOM。 以下是用于创建自定义物料清单（BOM）文件的插件设置窗口（在 Linux 上）：

image::images/zh/bom-netlist-tab.png[alt="bom-netlist-tab_png", scaledwidth="80%"]

样式表 bom2csv.xsl 的路径取决于系统。 目前用于 BOM 生成的最佳 XSLT 样式表称为 __bom2csv.xsl__。 您可以根据自己的需要自由修改它，如果您开发了一些非常有用的东西，请让它成为 KiCad 项目的一部分。

[[command-line-format-example-for-python-scripts]]
=== 命令行格式：python 脚本的示例

_python_ 的命令行格式如下：

python <脚本文件名> <输入文件名> <输出文件名>

在 Windows 下：

*python *.exe f:/kicad/python/my_python_script.py "%I" "%O"*

在 Linux 下：

*python /usr/local/kicad/python/my_python_script.py "%I" "%O"*

假设你的 PC 上安装了 python。

[[intermediate-netlist-structure]]
=== 中间网表结构

此示例提供了网表文件格式的概念。

---------------------------------------------------------------
<?xml version="1.0" encoding="utf-8"?>
<export version="D">
  <design>
    <source>F:\kicad_aux\netlist_test\netlist_test.sch</source>
    <date>29/08/2010 21:07:51</date>
    <tool>eeschema (2010-08-28 BZR 2458)-unstable</tool>
  </design>
  <components>
    <comp ref="P1">
      <value>CONN_4</value>
      <libsource lib="conn" part="CONN_4"/>
      <sheetpath names="/" tstamps="/"/>
      <tstamp>4C6E2141</tstamp>
    </comp>
    <comp ref="U2">
      <value>74LS74</value>
      <libsource lib="74xx" part="74LS74"/>
      <sheetpath names="/" tstamps="/"/>
      <tstamp>4C6E20BA</tstamp>
    </comp>
    <comp ref="U1">
      <value>74LS04</value>
      <libsource lib="74xx" part="74LS04"/>
      <sheetpath names="/" tstamps="/"/>
      <tstamp>4C6E20A6</tstamp>
    </comp>
    <comp ref="C1">
      <value>CP</value>
      <libsource lib="device" part="CP"/>
      <sheetpath names="/" tstamps="/"/>
      <tstamp>4C6E2094</tstamp>
    <comp ref="R1">
      <value>R</value>
      <libsource lib="device" part="R"/>
      <sheetpath names="/" tstamps="/"/>
      <tstamp>4C6E208A</tstamp>
    </comp>
  </components>
  <libparts/>
  <libraries/>
  <nets>
    <net code="1" name="GND">
      <node ref="U1" pin="7"/>
      <node ref="C1" pin="2"/>
      <node ref="U2" pin="7"/>
      <node ref="P1" pin="4"/>
    </net>
    <net code="2" name="VCC">
      <node ref="R1" pin="1"/>
      <node ref="U1" pin="14"/>
      <node ref="U2" pin="4"/>
      <node ref="U2" pin="1"/>
      <node ref="U2" pin="14"/>
      <node ref="P1" pin="1"/>
    </net>
    <net code="3" name="">
      <node ref="U2" pin="6"/>
    </net>
    <net code="4" name="">
      <node ref="U1" pin="2"/>
      <node ref="U2" pin="3"/>
    </net>
    <net code="5" name="/SIG_OUT">
      <node ref="P1" pin="2"/>
      <node ref="U2" pin="5"/>
      <node ref="U2" pin="2"/>
    </net>
    <net code="6" name="/CLOCK_IN">
      <node ref="R1" pin="2"/>
      <node ref="C1" pin="1"/>
      <node ref="U1" pin="1"/>
      <node ref="P1" pin="3"/>
    </net>
  </nets>
</export>
---------------------------------------------------------------

[[general-netlist-file-structure]]
==== 一般网表文件结构

中间网表占五个部分。

* “标题” 部分。
* “元件” 部分。
* “库元件” 部分。
* “库” 部分。
* “网” 部分。

文件内容具有分隔符 <export>

--------------------
<export version="D">
...
</export>
--------------------

[[the-header-section]]
==== “标题” 部分

标题具有分隔符 <design>

-----------------------------------------------------------
<design>
<source>F:\kicad_aux\netlist_test\netlist_test.sch</source>
<date>21/08/2010 08:12:08</date>
<tool>eeschema (2010-08-09 BZR 2439)-unstable</tool>
</design>
-----------------------------------------------------------

此部分可被视为批注部分。

[[the-components-section]]
==== “元件” 部分

元件部分具有分隔符 <components>

-------------------------------------
<components>
<comp ref="P1">
<value>CONN_4</value>
<libsource lib="conn" part="CONN_4"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>4C6E2141</tstamp>
</comp>
</components>
-------------------------------------

本节包含原理图中的元件列表。 每个元件都是这样描述的：

-------------------------------------
<comp ref="P1">
<value>CONN_4</value>
<libsource lib="conn" part="CONN_4"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>4C6E2141</tstamp>
</comp>
-------------------------------------

[width="100%", cols="37%,63%"]
|=======================================================================
|*libsource* |找到此元件的库的名称。

|*part* |此库中的组件名称。

|*sheetpath* |层次结构中工作表的路径：标识工作表
在完整的原理图层次结构中。

|*tstamps (time stamps)* |原理图文件的时间戳。

|*tstamp (time stamp)* |元件的时间戳。
|=======================================================================

[[note-about-time-stamps-for-components]]
===== 关于元件的时间戳的注意事项

要识别网表中的元件，从而识别板上，时间戳参考对每个元件都是唯一的。 然而，KiCad 提供了一种辅助方法来识别元件，该元件是电路板上相应的占位面积。 这允许重新批注原理图项目中的元件，并且不会丢失元件与其占用空间之间的链接。

时间戳是原理图项目中每个元件或工作表的唯一标识符。但是, 在复杂的层次结构中, 同一工作表多次使用, 因此此工作表包含具有相同时间戳的元件。

复杂层次结构中的给定工作表具有唯一标识符：其 sheetpath。 给定元件（在复杂层次结构内）具有唯一标识符：sheetpath + 其 tstamp

[[the-libparts-section]]
==== “库部件” 部分

库部件部分具有分隔符 <libparts>，并且此部分的内容在原理图库中定义。 库部件部分包含

* 允许的封装名称(名称使用通配符)以 <fp> 为分隔符。
* 库分隔符中定义的字段 <fields>。
* 引脚列表分隔 <pins>。

--------------------------------------------------
<libparts>
<libpart lib="device" part="CP">
  <description>Condensateur polarise</description>
  <footprints>
    <fp>CP*</fp>
    <fp>SM*</fp>
  </footprints>
  <fields>
    <field name="Reference">C</field>
    <field name="Valeur">CP</field>
  </fields>
  <pins>
    <pin num="1" name="1" type="passive"/>
    <pin num="2" name="2" type="passive"/>
  </pins>
</libpart>
</libparts>
--------------------------------------------------

类似 <pin num="1" type="passive"/> 的线路也给出了电气引脚类型。可能的电气引脚类型有

[width="94%", cols="25%,75%"]
|================================================================
|Input |输入引脚
|Output |输出引脚
|Bidirectional |输入或输出
|Tri-state |总线输入/输出
|Passive |无源元件的结束
|Unspecified |未知电气类型
|Power input |单元件电源输入引脚
|Power output |电源输出引脚作为稳压器输出
|Open collector |模拟比较器中常见的开路集电极输出
|Open emitter |有时在逻辑中找到开放发射器输出。
|Not connected |必须在原理图中保持未连接状态
|================================================================

[[the-libraries-section]]
==== “库” 部分

库部分具有分隔符<libraries>。 本节包含项目中使用的原理图库列表。

------------------------------------------------
<libraries>
  <library logical="device">
    <uri>F:\kicad\share\library\device.lib</uri>
  </library>
  <library logical="conn">
    <uri>F:\kicad\share\library\conn.lib</uri>
  </library>
</libraries>
------------------------------------------------

[[the-nets-section]]
==== “网” 部分

“网” 部分具有分隔符 <nets>。本节包含原理图的 “连接”。

-----------------------------
<nets>
  <net code="1" name="GND">
    <node ref="U1" pin="7"/>
    <node ref="C1" pin="2"/>
    <node ref="U2" pin="7"/>
    <node ref="P1" pin="4"/>
  </net>
  <net code="2" name="VCC">
    <node ref="R1" pin="1"/>
    <node ref="U1" pin="14"/>
    <node ref="U2" pin="4"/>
    <node ref="U2" pin="1"/>
    <node ref="U2" pin="14"/>
    <node ref="P1" pin="1"/>
  </net>
</nets>
-----------------------------

本节列出了原理图中的所有网络。

可能的网络包含以下内容。

--------------------------
<net code="1" name="GND">
  <node ref="U1" pin="7"/>
  <node ref="C1" pin="2"/>
  <node ref="U2" pin="7"/>
  <node ref="P1" pin="4"/>
</net>
--------------------------

[width="77%", cols="20%,80%"]
|================================================
|net code |是此网络的内部标识符
|name |是此网络的名称
|node |给出一个连接到该网络的引脚引用
|================================================

[[more-about-xsltproc]]
=== 有关 xsltproc 的更多信息

请参阅页面：_http://xmlsoft.org/XSLT/xsltproc.html_

[[introduction-7]]
==== 简介

xsltproc 是一个命令行工具，用于将 XSLT 样式表应用于 XML 文档。 虽然它是作为 GNOME 项目的一部分开发的，但它可以独立于 GNOME 桌面运行。

从命令行调用 xsltproc，其中包含要使用的样式表的名称，后跟要应用样式表的文件的名称。 如果提供的文件名是 - ，它将使用标准输入。

如果样式表包含在带有样式表处理指令的 XML 文档中，则不需要在命令行中命名样式表。xsltproc 将自动检测包含的样式表并使用它。 默认情况下，输出为 __stdout__。 您可以使用 -o 选项指定要输出的文件。

[[synopsis]]
==== 简介

---------------------------------------------------------------------------
xsltproc [[-V] | [-v] | [-o *file* ] | [--timing] | [--repeat] |
[--debug] | [--novalid] | [--noout] | [--maxdepth *val* ] | [--html] |
[--param *name* *value* ] | [--stringparam *name* *value* ] | [--nonet] |
[--path *paths* ] | [--load-trace] | [--catalogs] | [--xinclude] |
[--profile] | [--dumpextensions] | [--nowrite] | [--nomkdir] |
[--writesubtree] | [--nodtdattr]] [ *stylesheet* ] [ *file1* ] [ *file2* ]
[ *....* ]
---------------------------------------------------------------------------

[[command-line-options]]
==== 命令行选项

_-V_ o _--version_

显示使用的 libxml 和 libxslt 的版本。

_-v_ o _--verbose_

输出 xsltproc 在处理样式表和文档时采取的每个步骤。

_-o_ o _--output file_

直接输出到名为 __file__ 的文件。对于多个输出，也称为 _chunking_，-o directory/ 将输出文件定向到指定的目录。该目录必须已存在。

_--timing_

显示用于解析样式表，解析文档和应用样式表并保存结果的时间。以毫秒显示。

_--repeat_

运行转换20次。用于定时测试。

_--debug_

输出转换后文档的 XML 树，以进行调试。

_--novalid_

跳过加载文档的 DTD。

_--noout_

不输出结果。

_--maxdepth value_

在 libxslt 断定它处于无限循环之前调整模板堆栈的最大深度。 默认值为500。

_--html_

输入文档是 HTML 文件。

_--param name value_

将名称 _name_ 和值 _value_ 的参数传递给样式表。 您可以传递多个名称/值对，最多为32.如果传递的值是字符串而不是节点标识符，请改用 --stringparam。

_--stringparam name value_

传递名称 _name_ 和值 _value_ 的参数，其中 _value_ 是字符串而不是节点标识符。（注意：字符串必须是utf-8。）

_--nonet_

不要使用互联网来获取 DTD，实体或文档。

_--path paths_

使用 _paths_ 指定的文件系统路径的列表（由空格或列分隔）来加载 DTD，实体或文档。

_--load-trace_

向 stderr 显示处理期间加载的所有文档。

_--catalogs_

使用 SGML_CATALOG_FILES 中指定的 SGML 目录来解析外部实体的位置。默认情况下，xsltproc 查找 XML_CATALOG_FILES 中指定的目录。如果未指定，则使用 /etc/xml/catalog。

_--xinclude_

使用 Xinclude 规范处理输入文档。有关这方面的更多详细信息，请参阅 Xinclude 规范：http://www.w3.org/TR/xinclude/[http://www.w3.org/TR/xinclude/]

_--profile --norman_

输出分析信息，详细说明样式表的每个部分所花费的时间。这在优化样式表性能时很有用。

_--dumpextensions_

将所有已注册扩展名的列表转储到 stdout。

_--nowrite_

拒绝写入任何文件或资源。

_--nomkdir_

拒绝创建目录。

_--writesubtree path_

仅允许在 _path_ 子树内写入文件。

_--nodtdattr_

不要从文档的 DTD 应用默认属性。

[[xsltproc-return-values]]
==== Xsltproc 返回值

xsltproc 返回一个状态编号，在脚本中调用它时非常有用。

0: 正常

1: 无参数

2: 参数太多

3: 未知选项

4：无法解析样式表

5: 样式表中的错误

6：其中一个文件出错

7: 不支持的 xsl: 输出方法

8：字符串参数包含引号和双引号

9: 内部处理错误

10：通过终止消息停止处理

11：无法将结果写入输出文件

[[more-information-about-xsltproc]]
==== 有关 xsltproc 的更多信息

libxml 网页：http://www.xmlsoft.org/[http://www.xmlsoft.org/]

W3C XSLT 页面：http://www.w3.org/TR/xslt[http://www.w3.org/TR/xslt]

:experimental:

[[simulator]]
== 仿真器 ==

KiCad provides an embedded electrical circuit simulator using http://ngspice.sourceforge.net[ngspice] as the simulation engine.

使用模拟器时，您可能会发现官方的 _pspice_ 库很有用。 它包含用于模拟的公共符号，如电压/电流源或晶体管，其引脚编号与 ngspice 节点顺序规范相匹配。

还有一些演示项目来说明模拟器的功能。 您将在 _demos/simulation_ 目录中找到它们。

=== 分配模型

在启动模拟之前，元件需要分配 Spice 模型。

即使元件由多个单元组成，每个元件也只能分配一个模型。 在这种情况下，第一个单元应该具有指定的模型。

”无源模型” 参考匹配 Spice 表示法中的器件类型的无源元件（_R*_ 表示电阻器，_C*_ 表示电容器，_L*_ 表示电感器）将隐式分配模型并使用值字段 确定他们的属性。

[NOTE]
请记住，在 Spice 表示法中，“M” 代表 milli，“Meg” 代表 mega。 如果您更喜欢使用 “M” 来表示超级前缀，您可以在（模拟设置，模拟设置对话框）中请求这样做。

Spice 模型信息作为文本存储在符号字段中，因此您可以在符号编辑器或原理图编辑器中定义它。 打开符号属性对话框，然后单击 _编辑 Spice 模型_ 按钮以打开 Spice 模型编辑器 对话框。

Spice 模型编辑器 对话框有三个对应于不同模型类型的选项卡。 所有模型类型共有两个选项：

[width="90%", cols="30%a,70%a"]
|====
|禁用模拟的符号
|选中时，元件将从模拟中排除。
|备用节点序列
|允许用户将符号引脚覆盖为模型节点映射。
要定义不同的映射，请按模型预期的顺序指定引脚编号。

'例子：'+
____
“* 连接：”+
“* 1: 非反相输入” +
“* 2: 反相输入” +
“* 3: 正电源” +
“* 4: 负电源” +
“* 5: 输出” +
“.子电路 tl071 1 2 3 4 5”
____

image::images/opamp_symbol.png[alt="通用运算放大器符号"]

要将符号引脚与上面显示的 Spice 模型节点相匹配，需要使用具有值的备用节点序列选项："1{nbsp}3{nbsp}5{nbsp}2{nbsp} 4"。 它是与 Spice 模型节点顺序对应的引脚编号列表。
|====

==== 无源

_无源_ 选项卡允许用户将无源器件模型（电阻，电容或电感）分配给元件。 这是一个很少使用的选项，因为通常被动元件的模型分配了 _模拟无源模型，隐形_ ，除非元件引用与实际设备类型不匹配。

[NOTE]
明确定义的被动设备模型优先于隐式分配的模型。 这意味着一旦分配了被动设备模型，在模拟期间不会考虑参考和值字段。 当指定的模型值与原理图纸上显示的模型值不匹配时，可能会导致混乱的情况。

image::images/sim_model_passive.png[alt="无源设备模型编辑器选项卡"]

[width="90%", cols="30%a,70%a"]
|====
|类型
|选择器件类型（电阻，电容或电感）。
|值
|定义器件属性（电阻，电容或电感）。 值
可以使用常见的 Spice 单元前缀（如文本输入字段下方列出的）和
应该使用点作为小数点分隔符。 请注意，Spice 不正确
解释在值中交织的前缀（例如 1k5）。
|====

==== 模型

_Model_ 选项卡用于分配外部库文件中定义的半导体或复杂模型。 Spice 模型库通常由设备制造商提供。

主文本小部件显示所选的库文件内容。 将模型描述放在库文件中是常见的做法，包括节点顺序。

image::images/sim_model_subckt.png[alt="半导体器件型号编辑器选项卡"]

[width="90%", cols="30%a,70%a"]
|====================
|文件
|Spice 库文件的路径。 该文件将由模拟器使用，
因为它是使用 ._include_ 指令添加的。
|型号
|所选设备型号。 选择文件后，列表将填充可用
模型可供选择。
|类型
|选择型号类型（子电路，BJT，MOSFET 或二极管）。 通常是设定的
选择模型时自动选择。
|====================

==== 源

_Source_ 选项卡用于分配电源或信号源模型。 有两个部分：“DC/AC 分析” 和“转换分析”。 每个都定义了相应模拟类型的源参数。

_Source type_ 选项适用于所有模拟类型。

image::images/sim_model_source.png[alt="源模型编辑器选项卡"]

有关源的更多详细信息，请参阅 http://ngspice.sourceforge.net/docs/ngspice-27-manual.pdf[ngspice文档] ，第4章（电压和电流源）。

[[sim-directives]]
=== Spice 指令

It is possible to add Spice directives by placing them in text fields on a schematic sheet. This approach is convenient for defining the default simulation type. This functionality is limited to Spice directives starting with a dot (e.g. `.tran 10n 1m`), it is not possible to place additional components using text fields.

=== 仿真

要启动模拟，请在原理图编辑器窗口中选择菜单 _工具->仿真_ 打开 _Spice仿真_ 对话框。

image::images/sim_main_dialog.png[alt="主仿真对话框"]

该对话框分为几个部分：

* 《模拟-工具栏，工具栏》
* 《模拟面板, 绘图面板》
* 《模拟输出控制台, 输出控制台》
* 《模拟信号列表，信号列表》
* 《模拟游标列表，游标列表》
* 《模拟面板, 绘图面板》

==== 菜单

[[sim-menu-file]]
===== 文件
[width="90%", cols="30%,70%"]
|====
|新绘制 | 在绘图面板中创建一个新选项卡。
|打开工作簿 | 打开绘制信号列表。
|保存工作簿 | 保存绘制信号列表。
|另存为图像 | 将活动图导出为 .png 文件。
|另存为 .csv 文件 | 将活动绘图原始数据点导出到 .csv 文件。
|退出模拟 | 关闭对话框。
|====

[[sim-menu-simulation]]
===== 仿真
[width="90%", cols="30%,70%"]
|====
|运行模拟 | 使用当前设置执行模拟。
|添加信号...... | 打开一个对话框以选择要绘制的信号。
|原理图探测 | 启动原理图 “模拟探针工具，探针” 工具。
|调整元件值 | 启动 “模拟调谐工具，调谐” 工具。
|显示 SPICE 网表... | 打开一个对话框，显示生成的网表
模拟电路。
|设置... | 打开 “模拟设置，模拟设置对话框”。
|====

[[sim-menu-view]]
===== 视图
[width="90%", cols="30%,70%"]
|====
|缩小 | 缩小活动图。
|适合屏幕 | 调整缩放设置以显示所有绘图。
|显示网格 | 切换网格可见性。
|显示长度 | 切换图表图例可见性。
|====

[[sim-toolbar]]
==== 工具栏
image::images/sim_main_toolbar.png[alt="模拟对话框顶部工具栏"]
顶部工具栏提供对最常执行的操作的访问。

[width="90%", cols="30%,70%"]
|====
|运行/停止模拟 | 启动或停止模拟。
|添加信号 | 打开一个对话框以选择要绘制的信号。
|探针 | 启动原理图 “模拟探针工具，探针” 工具。
|调谐 | 启动 ”模拟调谐工具，调谐“ 工具。
|设置 | 打开 “模拟设置，模拟设置对话框”。
|====

[[sim-plot-panel]]
==== 绘图面板
将模拟结果可视化为图。 可以在单独的选项卡中打开多个图，但只有在执行模拟时才会更新活动图。 这样就可以比较不同运行的模拟结果。

可以使用 “模拟菜单视图，视图” 菜单切换网格和图例可见性来自定义绘图。 当图例可见时，可以拖动它来改变其位置。

绘图面板交互：

* 滚动鼠标滚轮放大/缩小
* 右键单击打开上下文菜单以调整视图
* 绘制选择矩形以放大所选区域
* 拖动光标以更改其坐标

[[sim-output-console]]
==== 输出控制台
输出控制台显示来自模拟器的消息。 建议检查控制台输出以确认没有错误或警告。

[[sim-signals-list]]
==== 信号列表
显示活动图中显示的信号列表。

信号列表交互:

* 右键单击打开上下文菜单以隐藏信号或切换光标
* 双击以隐藏信号

[[sim-cursors-list]]
==== 游标列表
显示游标列表及其坐标。 每个信号可以显示一个光标。 使用 “模拟信号列表，信号” 列表设置游标可见性。

[[sim-tune-panel]]
==== 调谐面板
显示使用 “模拟调谐工具，调谐“ 工具选取的元件。 调谐面板允许用户快速修改元件值并观察它们对模拟结果的影响 - 每次更改元件值时，都会重新运行模拟并更新图形。

对于每个元件，有一些控件关联：

* 顶部文本字段设置最大元件值。
* 中间文本字段设置实际的元件值。
* 底部文本字段设置最小元件值。
* 滑块允许用户以平滑的方式修改元件值。
* _Save_ 按钮将原理图上的元件值修改为使用滑块选择的元件值。
* _X_ 按钮从调谐面板中删除元件并恢复其原始值。

三个文本字段识别 Spice 单元前缀。

[[sim-tuner-tool]]
==== 调谐工具
调谐器工具允许用户选择要调整的元件。

要选择要调整的元件，请在工具处于活动状态时单击原理图编辑器中的一个元件。 所选元件将出现在 “模拟调谐工具，调谐” 面板中。 只能调整被动元件。

[[sim-probe-tool]]
==== 探针工具
探针工具提供了一种用户友好的方式来选择用于绘图的信号。

要向绘图添加信号，请在工具处于活动状态时单击原理图编辑器中的相应导线。

[[sim-settings]]
==== 仿真设置

image::images/sim_settings.png[alt="模拟设置对话框"]

模拟设置对话框允许用户设置模拟类型和参数。有四个选项卡：

* 交流
* 直流转换
* 短暂的
* 自定义

前三个选项卡提供可以指定模拟参数的表单。 最后一个选项卡允许用户键入自定义 Spice 指令以设置模拟。 有关仿真类型和参数的更多信息，请参见 http://ngspice.sourceforge.net/docs/ngspice-27-manual.pdf[ngspice文档] ，第1.2章。

配置模拟的另一种方法是在原理图上的文本字段中键入 “模拟指令，Spice 指令”。 与模拟类型相关的任何文本字段指令都会被对话框中选择的设置覆盖。 这意味着一旦开始使用模拟对话框，该对话框将覆盖原理图指令，直到重新打开模拟器。

所有模拟类型共有两个选项：
[width="90%", cols="30%,70%"]
|====
|调整被动符号值 | 替换被动符号值以转换常见
元件值符号表示 Spice 表示法。
|为 .include 库指令添加完整路径 | Prepend Spice 模型库
文件名为完整路径。 通常，ngspice 需要完整路径才能访问
库文件。
|====