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Design-Rule Checking |
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The incremental design-rule checker uses connectivity information to detect violations. This use of network information helps the designer to debug circuit connectivity. For example, if two overlapping nodes are not joined by an arc, they may be considered to be in violation, even if their geometry looks right. This is because the checker looks for unconnected layers that are too close. To examine and modify the spacing limits between unconnected layers, use the Edit Unconnected Rules subcommand of the DRC command of the Tools menu. More information on text editing can be found in the "Text Windows" section of Chapter 4.
The incremental design-rule checker has a separate set of rules for connected layers. Therefore, components that are too close together, yet connected elsewhere in the circuit, will be understood to be correct. To examine and modify the spacing limits between connected layers, use the Edit Connected Rules subcommand.
The user should be warned that the incremental design-rule checker does have some shortcomings. First, it does not examine hierarchy. This means that if a facet instance is used in a circuit, the design-rule checker does not examine its contents to see how that interacts with other layout surrounding the instance. Second, the design-rule checker has a simple set of distance rules for each layer, depending on whether or not the layers are electrically connected. This means that more complex rules involving combinations of layers are not checked. The user must consider the incremental design-rule checker to be an assistant to design, rather than the final word on circuit validity. For a more rigorous analysis, use the batch DRC or the Dracula facility.
By default, the incremental design-rule checker is on. To turn it off, use the Turn DRC Off subcommand of the DRC command of the Tools menu. While the tool is off, Electric keeps track of all facets that change. When the tool is turned back on (with the same menu entry which now reads Turn DRC On) it rechecks all of those changed facets. Thus, the design-rule checker can be made into a "batch" tool by keeping it off until circuit layout is complete.
The incremental design-rule checker has two styles in which it can work. By default, each violation is simply displayed in the messages window, and no acknowledgement is expected. The subcommand Highlight Errors causes the design-rule checker to work interactively, where each violation is highlighted and the system pauses and awaits further instructions. Uncheck the menu entry to disable this interactive mode.
![]() | While in the interactive mode, a dialog will be presented when any design-rule violation is detected. The possible responses to this dialog are to continue checking (the "OK" button), to terminate this interactive style and continue checking silently (the "Continue Silently" button), to remember this violation and ignore it in subsequent checking (the "Ignore this error" button), and to terminate checking (the "Stop Checking" button). |
Because errors are not repeated once they are detected, it is useful to recheck an entire facet to see what errors remain. Use the Recheck Facet subcommand to run the design-rule checker over the current facet. The command Recheck Entire Facet works in the same way, except that any violations that were ignored (with the "Ignore this error" button) are also considered (the list of ignored violations is deleted).
The batch design-rule checker uses the same rules and techniques
as the incremental checker, but it is able to check hierarchy.
To run it, use the Batch Check... subcommand of the DRC command
of the Tools menu.
Select the "Check" button to begin checking (you can abort
checking by typing the interrupt key
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Another design-rule checking facility that is available in Electric is an interface with the Dracula design-rule checker. This interface requires a circuit description and a set of design rules. Electric knows the design-rules (currently only for the MOSIS CMOS technology) and is able to generate the proper circuit description (a CIF file). To generate these files, use the Write Dracula Deck subcommand.
To see the set of Dracula design rules for the current technology, use the Edit Dracula Rules subcommand. This will display the rules in an edit window. Note that since only the "mocmos" technology has valid design rules, this command will present an empty window when run in other technologies. However, you can create your own design-rules for any technology. Consult the manufacturer for a description of their design-rules.
To help guide the Dracula design-rule checker, a "cloaking" layer can be placed over areas that are not to be examined. This cloaking layer is created by using the DRC Exclusion subcommand of the New Special Object command of the Edit menu. The node that is placed produces a layer called "DRC" in the Dracula file, which causes the circuitry underneath to be ignored.
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