Chapter IX: TOOLS

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VHDL Compiler

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The VHDL compiler translates structural VHDL code into netlists. It can generate a number of different netlist formats including ones for the simulator and the silicon compiler. It can compile disk files or textual facets of the appropriate view. Although the simulator and the silicon compiler systems can drive the VHDL compiler directly, users can request compilation for specific purposes.

Use the Compile for Silicon Compiler, Compile for Simulation, Compile for RNL, Compile for RSIM, and Compile for SILOS subcommands of the VHDL Compiler command of the Tools menu to generate appropriate format netlists. By default, the compiler reads VHDL from the "vhdl" view of the facet in the current window and writes netlists to appropriate "netlist" views of this facet. By unchecking the VHDL Stored in Facet subcommand, the VHDL is taken from the file "XXX.vhdl", where XXX is the current cell name. By unchecking the Netlist Stored in Facet subcommand, the netlist is written to the file "XXX.sci" (for the silicon compiler), "XXX.net" (for the simulator, RNL, and RSIM), or "XXX.sil" (for SILOS) where XXX is the current cell name. Recheck these subcommands to locate the text in the facets.

Another feature of the VHDL compiler is its ability to generate VHDL from a schematic or layout. Use the Make VHDL command of the View menu to convert the current facet into VHDL. Note that the state of the VHDL Stored in Facet subcommand of the VHDL Compiler command of the Tools menu determines whether this VHDL is written to disk or a facet.


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