Chapter VII: DESIGN ENVIRONMENTS

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The MOSIS CMOS Submicron Technology

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The MOSIS CMOS submicron technology describes a scalable CMOS process that is fabricated by the MOSIS project of the University of Southern California. To obtain this technology, use the Change Current Technology command of the Technology menu and select "mocmossub".

Figure 7.2

This technology has 4 metal layers, but can also be used for 3-metal processes by using the MOSIS CMOS Submicron: 3-Metal Rules subcommand of the Parametrize Technology command of the Technology menu.

By default, this technology describes a p-well process. However, it is possible to switch to an n-well process with the MOSIS CMOS Submicron: n-Well subcommand of the Parametrize Technology command of the Technology menu. This command switches layer usage and renames the transistors, contacts, and arcs so that an n-well technology is in effect.

Be warned that Electric always starts up with this as a p-well technology. Therefore, if you have switched to n-well and created a library, you must switch each time you rerun the system before reading that library. The best solution to this situation is to always use the default p-well version of the technology and only switch to n-well before chip fabrication.


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