Chapter XI: MENU SUMMARY

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The Tools Menu

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Figure 11.10

This menu is a collection of submenus that controls the different analysis and synthesis tools in Electric. For analysis, there are Design-Rule Checkers, a simulator, many simulation interfaces, and a network consistency checker. For synthesis, there are routers, PLA generators, a VHDL compiler, and a silicon compiler place-and-route system.

DRC

Figure 11.23
This submenu controls the design-rule checkers. There is an incremental system which watches all design and displays warnings where appropriate. There is also a batch checker and an interface to the Dracula DRC system.

Turn DRC Off This command disables the incremental actions of the design-rule checker. This menu entry changes to Turn DRC On to reenable the system. When the system is turned back on, it will check all facets that have been modified since it was turned off. If this takes too long, it can be aborted with interrupt key (CMD-. on the Macintosh, ^C elsewhere).
Highlight Errors
This command tells the design-rule checker to pause at each violation and highlight the offending geometry. You then have the option to acknowledge or ignore this error and you can terminate checking or continue silently. Uncheck the menu entry to disable highlighting.
Figure 9.1
Recheck Facet This command tells the design-rule checker to reexamine everything in the current facet.
Recheck Entire Facet This command tells the design-rule checker to throw away the list of ignored errors that may have accumulated with the Highlight Errors option above, and reexamine everything in the current facet.
Edit Connected Rules This command allows the design rules to be examined and modified for all layer combinations, where the two layers are electrically connected.
Edit Unconnected Rules This command allows the design rules to be examined and modified for all layer combinations, where the two layers are not electrically connected.

 
Batch Check...
This command presents a dialog for running a thorough design-rule check. Use the "Check" button to begin checking. Use the interrupt key to abort checking (CMD-. on the Macintosh, ^C elsewhere). When done, use the "Show First Error", "Show Next Error", and "Show Prev Error" buttons to move through the list. Use the "Done" button to quit the dialog.
Figure 9.2

 
Write Dracula Deck This command tells the design-rule checker to produce an input deck for the Dracula design-rule checker. At the current time, only layout in the MOSIS CMOS (mocmos) technology can be checked in this manner. However, with the Edit Dracula Rules command below, rule sets may be defined for any technology.
Edit Dracula Rules This command allows you to modify the design rules for the Dracula design-rule checker. The rules must contain the lines: "PRIMARY =" and "INDISK = " so that the deck generator can substitute the proper file names. Note that only the MOSIS CMOS (mocmos) technology has Dracula design rules, so to create them for a new technology, the best solution is (1) use the Change Current Technology command from the Technology menu to switch to the MOCMOS technology, (2) edit the rules using this command, (3) select everything and use the Copy subcommand of the Text Edit command of the Edit menu to copy them, (4) close the text editing window, (5) use the Change Current Technology command from the Technology menu to switch to the desired technology, (6) edit the rules with this command, which displays a blank editing window, and (7) use the Paste subcommand of the Text Edit command from the Edit menu to recover the MOSIS CMOS rules. You can now edit these rules, which will be saved with your library.



Simulation

Figure 11.24
This submenu controls the gate-level simulator in Electric. You can control simulation, move up and down the hierarchy, control test vectors, and set simulation parameters.

Simulate... This command causes the current facet to be simulated. If the current facet is not a netlist, and the netlist associated with this facet is missing or out of date, the VHDL compiler is invoked to build a new one. If the current facet is not VHDL, and the VHDL associated with this facet is missing or out of date, it is generated from the schematic or layout. A waveform display is shown for viewing signal values.
Simulate, No Waveform Display... This command is the same as the Simulate... command above, except that it does not display a waveform window (simulation values can be entered directly onto arcs).

 
Annotate Delay Data
Figure 11.35
This command lets you select which of the sets of stimulus data to use. The stimulus data is acquired with the SDF subcommand of the Import command of the File menu.
Restore Signal Display Order This command restores the default set of signals in the waveform display, which is useful if they have been rearranged or if some signals were deleted.

 
Down Hierarchy... This command causes the simulation to descend the hierarchy to a lower level so that signals can be viewed there. You will be prompted with a list of lower levels to view.
Up Hierarchy This command causes the simulation to ascend to the next higher level of hierarchy.

 
Read Vectors from Disk This command causes a file of test vectors to be read from disk. You will be prompted for the file name.
Save Vectors to Disk This command causes the current set of test vectors to be saved to disk. You will be prompted for the file name.
Clear All Vectors This command erases all test vectors from the simulation.

 
Resimulate Each Change This command, when checked, causes the simulator to resimulate each time any change is made. Uncheck this command to delay redisplay and resimulation.
Auto-Advance Time This command, when checked, causes the simulator to advance time after each change so that the simulation is now at the end of the effect of the change. In the waveform window, the main time cursor is advanced. Uncheck this command to keep time from advancing after test vector changes.
MultiState Display This command, when checked, causes the simulator to display multiple state strengths with different colors and/or textures. Uncheck this command to view only two-state (on or off) simulation display.



Simulation Interface

Figure 11.25
This submenu allows input decks to be written for many different simulators. For all except SPICE, only a deck is written. For SPICE, it is possible to read the output back into Electric for display as a plot.

Write SPICE Deck This command generates an input deck for the SPICE circuit-level simulator. Since SPICE is not an interactive system, it is necessary to specify inputs and outputs in the circuit. This is done by placing Source and Meter components (from the New Analog Component submenu of the Edit menu), parametrizing them with the actual SPICE message, and connecting them to the circuitry. It is also necessary to specify Transient or DC analysis by placing an appropriate Source component in the facet.
SPICE Options... This command allows many SPICE options to be controlled, for example, the SPICE format (SPICE 2, SPICE 3, or HSPICE), the SPICE level (1, 2, or 3), the option of including parasitics in the deck, the use of Electric node names in the deck (HSPICE only), whether or not to run SPICE after generating the deck (UNIX systems only), where to find model cards (on disk, or use the built-in ones settable with the next command), whether to use a file of trailer cards, and whether to use files of SPICE descriptions for any facet in the current library.
Figure 9.3
Built-in Model Cards
Figure 11.26
This command allows you to edit the model cards for any of the three SPICE levels.

Plot SPICE Listing This command reads the output of a SPICE run and produces a waveform plot. The plot is actually a facet composed of Artwork components, and its view is of type "simulation output".

 
Write ESIM Deck This command generates an input deck for the ESIM switch-level simulator (nMOS only, no timing).
Write RSIM Deck This command generates an input deck for the RSIM switch-level simulator (nMOS only).
Write RNL Deck This command generates an input deck for the RNL switch-level simulator (nMOS only, Lisp-like interface).
Write COSMOS Deck This command generates an input deck for the COSMOS switch-level simulator (MOS only).
Write MOSSIM Deck This command generates an input deck for the MOSSIM switch-level simulator (MOS only).

 
Write TEGAS Deck This command generates an input deck for the TEGAS/TEXSIM gate-level simulator.
Write SILOS Deck This command generates an input deck for the SILOS simulator.
Write PAL Deck This command generates an input deck for the Abel PAL generator/simulator.



PLA Generation

Figure 11.27
This command provides two different generators. Both will run faster if the design-rule checker is turned off. Either may be aborted with the interrupt key (CMD-. on the Macintosh, ^C elsewhere).

Make nMOS PLA This command prompts for a personality table and generates nMOS layout, complete with power and clocking. See the description of the PLA generator for a sample personality table.
Make MOSIS CMOS PLA This command prompts for two personality tables: the AND and the OR tables. It also offers options about the location of inputs and outputs. See the description of the PLA generator for a sample CMOS personality table.



VHDL Compiler

Figure 11.28
This submenu provides direct control of the VHDL compiler, which translates VHDL textual descriptions into netlists. Besides controlling which format netlist is generated, it is also possible to determine whether the netlist of the VHDL is to be stored in memory (in a facet) or on disk.

Compile for Silicon Compiler This command causes the VHDL in the current facet to be compiled into a netlist for the silicon compiler. If the current facet is not a VHDL view, the VHDL view is used. If VHDL disk files are being used instead of facets, the file "XXX.vhdl" is read, where XXX is the cell name of the current facet. If netlists are being written to disk, the file "XXX.sci" is written.
Compile for Simulation This command causes the VHDL in the current facet to be compiled into a netlist for simulation. If the current facet is not a VHDL view, the VHDL view is used. If VHDL disk files are being used instead of facets, the file "XXX.vhdl" is read, where XXX is the cell name of the current facet. If netlists are being written to disk, the file "XXX.net" is written.
Compile for RNL This command causes the VHDL in the current facet to be compiled into a RNL simulator netlist. If the current facet is not a VHDL view, the VHDL view is used. If VHDL disk files are being used instead of facets, the file "XXX.vhdl" is read, where XXX is the cell name of the current facet. If netlists are being written to disk, the file "XXX.net" is written.
Compile for RSIM This command causes the VHDL in the current facet to be compiled into a RSIM simulator netlist. If the current facet is not a VHDL view, the VHDL view is used. If VHDL disk files are being used instead of facets, the file "XXX.vhdl" is read, where XXX is the cell name of the current facet. If netlists are being written to disk, the file "XXX.net" is written.
Compile for SILOS This command causes the VHDL in the current facet to be compiled into a SILOS simulator netlist. If the current facet is not a VHDL view, the VHDL view is used. If VHDL disk files are being used instead of facets, the file "XXX.vhdl" is read, where XXX is the cell name of the current facet. If netlists are being written to disk, the file "XXX.sil" is written.

 
VHDL Stored in Facet This command, when checked, directs Electric to read and write VHDL to facets. When unchecked, the VHDL is located on disk. Besides the compile subcommands in this menu, the state of this switch also affects the Make VHDL command of the View menu, the Simulate... subcommand of the Simulation command of the Tools menu, and the Get Network for Current Facet subcommand of the Silicon Compiler command of the Tools menu.
Netlist Stored in Facet This command, when checked, directs Electric to read and write netlists to facets. When unchecked, the netlist is located on disk. Besides the compile subcommands in this menu, the state of this switch also affects the Simulate... subcommand of the Simulation command of the Tools menu and the Get Network for Current Facet subcommand of the Silicon Compiler command of the Tools menu.

 
Select Behavioral Library When compiling for simulation, behavioral models will be included if they are found in the current library. This command allows an alternate library to be searched for the models. Note that each model can be found in the "netlist-als-format" view of an appropriately named cell.



Silicon Compiler

Figure 11.29
This submenu is an extensive system for placing and routing standard cell libraries from a structural VHDL description. Simply run each command in sequence: select a library, obtain a netlist, set the number of rows, place, route, and make Electric layout.

Read MOSIS CMOS Library This command requests that the MOSIS CMOS standard cell library be used. See the "Silicon Compiler" section of Chapter 9 for a description of the cells in this library.
Get Network for Current Facet This command gets a netlist for the current facet. If the current facet is not a netlist, and the netlist associated with this facet is missing or out of date, the VHDL Compiler will be used to create a netlist. If the current facet is not VHDL, and the VHDL associated with this facet is missing or out of date, the VHDL will be generated from a schematic.
Set Number of Rows This command allows you to specify the number of rows of standard cells that the placement system will produce.
Do Placement This command computes the placement of standard cells.
Do Routing This command computes the routing among the placed standard cells.
Make Electric Layout This command generates final circuitry from the computed placement and routing. The design-rule checker is turned off during this step.

 
Issue Special Instructions This command allows you to communicate directly with the Silicon Compiler. Only those familiar with the system should do this (the other commands in this submenu handle standard functions without the need to know how the compiler works). If you do issue this command accidentally, use the "quit" command to exit the compiler.



Network

Figure 11.30
This submenu controls miscellaneous network functions, including a network consistency checking facility.

Show Network This command shows the equivalent to the currently highlighted network in all other windows. It also works for network names seleted in a text window. If this facet has been run through the network consistency checker, that information will be used.

 
Do Consistency Check This command compares the networks in the two facets being displayed.
Check Hierarchically This command tells the network consistency checker to examine the contents of facet instances, thus flattening the hierarchy before checking begins. Uncheck the menu entry to request examination of the current hierarchical level only.
Set First Equate In order to help the network consistency checker, it is possible to explicitly indicate two components from different facets that are equivalent. To do so, select a component from one facet and issue this command. Then select the equivalent component in the other facet and issue the next command.
Set Second Equate This command completes the specification of two equivalent components for the consistency checker. The currently highlighted node is recorded as equivalent to the node that was highlighted when the above command was issued.
Clear Equates This command erases the list of equivalent components.

 
Rip Bus Signals This command takes the currently selected bus wire and adds wire taps for each signal on the bus. The wires run perpendicular to the bus and are labeled with their signal.
Redo Network Numbering This command is not generally needed but may be useful if you suspect that the network information is incorrect.
Unify Power and Ground This command indicates that all power and ground ports should be considered to be electrically tied, regardless of their connectivity in the circuit. By default, this only happens in schematics, where the Power and Ground nodes appear. With this command, the unification happens in IC technologies also. The unchecked state causes unconnected networks to be regarded separately.
Unify All Like-Named Nets This command indicates that all networks with the same name are to be unified, regardless the nature of the circuit. Normally, only schematic facets have like-named networks electrically connected. When this menu entry is checked, even layout facets will have implicit connections through common network names.



Routing

Figure 11.31
This submenu controls a number of wire routing facilities.

Enable Auto-Stitching This command instructs the router to watch all subsequent layout activity and to place arcs wherever touching nodes create implicit connections. It is useful to issue this command before generating arrays, because the array may produce many implicit connections that this router will make explicit. The menu entry changes to Stop Auto-Stitching to disable the function.
Stitch Highlighted This does auto-stitching only in the currently highlighted area. The highlighted area is defined as the bounding rectangle of everything that is highlighted. A more precise way of defining a highlighted area is to use the rectangle select button to drag a rectangle on the screen.
Set Routing Arc
This command provides a dialog for selection of the type of arc to use in auto stitching. The default is to automatically determine the arc type to use from the ports. With this command, an alternate wire type can be specified. The "Use Default" button reverts to automatic arc selection.
Figure 9.5

 
Enable Mimic-Stitching This command instructs the router to watch all subsequent layout activity and to automatically create other arcs in similar locations whenever you create one by hand. The menu entry changes to Stop Mimic-Stitching to disable this function.

 
Maze-Route Selected This command runs the maze router in the selected area. All occurrences of the Unrouted wire will be replaced with real geometry.
Maze-Route Facet This command runs the maze router in the current facet. All occurrences of the Unrouted wire will be replaced with real geometry.

 
River-Route This command runs the river-router in the current facet. All occurrences of the Unrouted wire will be replaced with real geometry.

 
Unroute This command takes the currently selected network(s) and converts them to unrouted wires. After this command, you can maze-route or river-route the unrouted wires.
Get Unrouted Wire This command selects the unrouted wire so that subsequent wiring commands will use it. This is necessary in order to do maze and river-routing.



Compaction

Figure 11.39
This submenu controls the layout compactor.

Do Compaction This command compacts the layout in the current window to design-rule distances. It alternates horizontal and vertical compaction until no additional space can be saved.
Allow Spreading This command tells the compactor that it is allowed to spread the circuit where it is too close for the design rules.


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